Abstract: A method and apparatus for reducing latency in pipelined circuits that process dependent operations is presented. In order to reduce latency for dependent operations, a pre-accumulation register is included in an operation pipeline between a first operation unit and a second operation unit. The pre-accumulation register stores a first result produced by the first operation unit during a first operation. When the first operation unit completes a second operation to produce a second result, the first result stored in the pre-accumulation register is presented to the second operation unit along with the second result as input operands.

Abstract: The present invention provides a system and method for improving the performance of general purpose processors by expanding at least one source operand to a width greater than the width of either the general purpose register or the data path width. In addition, the present invention provides several classes of instructions which cannot be performed efficiently if the operands are limited to the width and accessible number of general purpose registers. The present invention provides operands which are substantially larger than the data path width of the processor by using a general purpose register to specify a memory address from which at least more than one, but typically several data path widths of data can be read. The present invention also provides for the efficient usage of a multiplier array that is fully used for high precision arithmetic, but is only partly used for other, lower precision operations.

Abstract: A method for storing a block of data consisting of N rows and M columns, which includes the step of transposing the block of data by 90° to thereby produce a transposed block of data consisting of M rows and N columns, and, the step of storing the transposed block of data. The transposed block of data is preferably retrieved by using one or more fetch commands, with the number of fetch commands required to retrieve the transposed block of data being less than the number of fetch commands required to retrieve the same data if stored in its original form, thereby reducing memory bandwidth. In a presently contemplated implementation, the block of data is a reference macroblock of decoded MPEG video data that is used in motion compensation operations, and each of the fetch commands is an A×B fetch command, where A represents the number of columns of data and B represents the number of rows of data to be fetched in response thereto, and wherein further, A>B.

Abstract: Disclosed are an image data processing method and apparatus for reading image data out of a memory and processing the image data, in which the memory stores image data representing an image as a collection of a plurality of partial images and from which the image data can be read out upon specifying image data in units of the partial images. If sequence information indicating the display sequence of the plurality of partial images of the image is stored in association with the image, then the partial images can be read out and displayed in accordance with the sequence information. By displaying completed partial images upon appending specific information thereto, it is possible to distinguish partial images whose display has been completed on a screen from partial images whose display has not been completed on the screen.

Abstract: A method and apparatus for visiting all stamps that are relevant to a two-dimensional convex polygonal object. The object is visited with a rectangular stamp, which contains one or more discrete sample points. A relevant location is one for which the object contains at least one of the stamp's sample points when the stamp is placed at that location. Stamp locations are discrete points that are separated vertically by the stamp's height, and horizontally by the stamp's width. The stamp may move to a nearby position, or to a previously saved position, as it traverses the object. The plane in which the object lies is partitioned into rectangular tiles, which are at least as wide and high as the stamp. The invention visits stamp locations in an order that respects tile boundaries—that is, it visits all locations within one tile before visiting any locations within another tile.

Abstract: A method and apparatus in a data processing system for updating a buffer containing display information used to display pixels from a first layer and a second layer on a display in the data processing system. Pixels from the first layer and pixels from the second layer are identified in a transparent region. The display information is updated in the buffer for pixels in the first layer in the transparent region. Correct display information is assigned to pixels in the second layer in the transparent region.

Abstract: A method and a system for buffer management is provided. The system includes a central processing unit, a multimedia chip, a buffer, a beginning register, an ending register, and a pause register. The beginning register is employed to store a beginning address of the buffer, and the ending register is used to storing an ending address of the buffer or buffer length. Content of the pause register is a data address associated with a command data. In addition, the pause register includes a pause code. When the pause code is equal to a first value, after the multimedia chip reads command data associated with the content of the pause register, reading is stopped, and the command data next to the command data are to be read in the next reading. When the pause code is equal to a second value, after the multimedia chip reads the command data associated with the content of the pause register, the multimedia chip continues to reads command data associated with the beginning register.

Abstract: First, link names of all the USB devices, that are connected to the system at that time, are retrieved, and a port is opened for one of the link names (S10, S20). Then, a command requesting a printer, that is connected to the subject port, to transmit device ID is issued, and a model name is extracted from device ID that is received in response to the command (S30-S50). Then, a serial number is retrieved from the subject link name (S60). Then, a port name such as “BRUSB001[PR1000]”, is created to include both the serial number and the model name (S70). The created port name is registered in S80, and the subject port that has been processed in S20-S80 is closed (S90).

Abstract: A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon Memory for storage. A a mode injection unit receives inputs from the Polygon Memory and communicates the mode information to one or more other processing units. The mode injection unit maintains status information identifying the information that is already cached and not sending information that is already cached, thereby reducing communication bandwidth.

Abstract: An object of the present invention is to provide an image processing apparatus in which a delay from start of image data input to start of coding is small, the capacity of a temporary storage device used for temporarily storing the image data to be coded is small, and the possibility of discarding the image data is low even when coding is delayed and, therefore, the image quality is hardly degraded. Since this apparatus is provided with a flag generator for generating control information according to the processing status, input/output of the image data in/from the temporary storage device is performed for each unit amount, and storage and coding of the image data are executed according to the control information.

Abstract: A semiconductor memory device of a high degree of freedom in column and a graphics display system using the semiconductor memory device as a mapping memory are provided. The semiconductor memory device according to the present invention is comprised of a plurality of memory arrays and each memory array is comprised of a plurality of memory cell groups. A plurality memory cell groups in each memory array are independently selected according to the information of a separate column address. Column decoders select the column of a corresponding memory array in response to common column addresses and first or second separate column addresses. The first or the second separate column addresses select one memory cell group among memory cell groups in each memory array. The common column addresses select predetermined numbers of columns in each memory cell group.

Abstract: An entertainment apparatus is configured to enable a program for an older version of the apparatus to be executed. In a normal mode, a main processing unit (MPU) operates as a main CPU, a graphics processor (GP) operates as a graphics processor, and an input/output subprocessor (IOP) operates as a subprocessor for input and output. In a compatible mode in which a program for an older version of the apparatus is executed, the IOP capable of executing the program for the older version of the apparatus operates as a main CPU, and the MPU and GP emulate a graphics processor for the older version of the apparatus.

Abstract: A method and apparatus for improving performance of an AGP device is provided. In one embodiment of the invention, a second-level cache is provided for a TLB, and part of the data or part of the address that is not otherwise used for determining a TLB entry is divided by a prime number to determine which TLB entry to allocate. One embodiment of the invention provides the ability to load multiple cache lines during a single memory access without incurring additional transfer, storage, or management complexities. The full number of bits of each memory access may be used to load cache lines. One embodiment of the invention loads multiple cache lines for translations of consecutive ranges of addresses. Since the translations included in the multiple cache lines cover consecutive ranges of addresses, the relationship between the multiple cache lines loaded for a single memory access is understood, and additional complexity for cache management is avoided.

Abstract: The present invention is a system and method that efficiently converts a linear configuration virtual memory address to a physical memory address via a tile XY coordinate configuration system. The system and method of the present invention facilitates access of tile configuration frame buffers in a physical memory by computer graphics applications that are designed to designate frame buffer addresses in a virtual linear configuration. A linear-address is converted to into a tile XY coordinate address. Then a memory stroing a descriptor table is utilized to identify a translation buffer base frame offset associated with the particular frame buffer comprising the information to be accessed. Based upon the translation buffer base frame offset, a tile offset into the actual frame buffer tile is generated. A translation buffer component maps a number of graphics tiles and determines the address of a physical memory location associated with a base pixel of a particular graphics tile.

Abstract: Methods for operating a frame buffer memory device are disclosed which provide for accelerated rendering of two-dimensional and three-dimensional images in a computer graphics system One disclosed operation is a method for compressing data to be transmitted from a controller to the memory device and then decompressing the data within the memory device once it has been transmitted and received.

Abstract: A system is described that is broadly directed to a system of integrated circuit components. The system comprises a plurality of nodes that are interconnected by communication links. A random access memory (RAM) is connected to each node. At least one functional unit is integrated into each node, and each functional unit is configured to carry out a predetermined processing function. Finally, each RAM includes a coherency mechanism configured to permit only read access to the RAM by other nodes, the coherency mechanism further configured to permit write access to the RAM only by functional units that are local to the node.

Abstract: A system and method for synchronization of video raster display outputs from multiple PC graphics subsystems to facilitate synchronized output onto multiple displays are disclosed. The system and method allow multiple graphics subsystems, in a single or multiple chassis, to be used to provide multiple synchronized view ports of a single 3D database or a wide desktop with reduced inter-monitor artifacts and interference.

Abstract: An AC plasma display device includes a pair of spaced apart first and second plates. The first plate bears electrodes each extending in a first direction, and the second plate bears paired first and second electrodes each extending in another direction perpendicular to the first direction. The paired first and second electrodes are divided into several groups. Further, the device includes first connecting lines connected to each other, each of which is associated with the first electrodes in one of the groups. Also provided are second connecting lines connected to each other, each of which is associated with the second electrodes in one of the groups. In addition, the device includes first pulse generators, each of which is associated with one of the first connecting lines and second pulse generators, each of which is associated with one of the second connecting lines.

Abstract: Routine processing for routine data, non-routine processing for routine data and general non-routine processing are to be processed efficiently. To this end, a main CPU has a CPU core having a parallel computational mechanism, a command cache and a data cache as ordinary cache units, and a scratch-pad memory SPR which is an internal high-speed memory capable of performing direct memory accessing (DMA) suited for routine processing. A floating decimal point vector processor (VPE) has an internal high-speed memory (VU-MEM) capable of DMA processing and is tightly connected to the main CPU to form a co-processor. The VPE has a high-speed internal memory (VU-MEM) capable of DMA processing. The DMA controller (DMAC) controls DMA transfer between the main memory and the SPR, between the main memory and the (VU-MEM) and between the (VU-MEM) and the SPR.

Abstract: A programmable processor that comprises a general purpose processor architecture, capable of operation independent of another host processor, having a virtual memory addressing unit, an instruction path and a data path; an external interface; a cache operable to retain data communicated between the external interface and the data path; at least one register file configurable to receive and store data from the data path and to communicate the stored data to the data path; and a multi-precision execution unit coupled to the data path. The multi-precision execution unit is configurable to dynamically partition data received from the data path to account for an elemental width of the data and is capable of performing group floating-point operations on multiple operands in partitioned fields of operand registers and returning catenated results. In other embodiments the multi-precision execution unit is additionally configurable to execute group integer and/or group data handling operations.