Patents Examined by Mahmoud Dahimene
  • Patent number: 9054244
    Abstract: A method is provided forming a predetermined irregular-surface pattern on a substrate. The method includes carrying out a plasma-etching process using a partly oxidized metal salt film having fine irregular-surface as a resist. In a first step, a metal salt film is formed on the substrate by coating a liquid material containing a metal salt. In a second step, a fine irregular-surface is formed on the metal salt film, and the metal salt film was converted into the resist by the partial oxidization. In a third step, a predetermined irregular-surface is formed on the substrate by carrying out the plasma-etching process to the substrate with the resist.
    Type: Grant
    Filed: January 5, 2011
    Date of Patent: June 9, 2015
    Assignee: LINTEC CORPORATION
    Inventors: Satoshi Naganawa, Takeshi Kondo
  • Patent number: 9053736
    Abstract: A method for manufacturing an aluminosilicate glass substrate for a hard disk of the present invention includes polishing an aluminosilicate glass substrate to be polished with a polishing composition that includes silica particles, a polymer having a sulfonic acid group, and water, wherein an adsorption constant of the polymer having the sulfonic acid group on aluminosilicate glass is 1.5 to 5.0 L/g. The polymer having the sulfonic acid group is preferably a polymer having an aromatic ring. The weight average molecular weight of the polymer having the sulfonic acid group is 3000 to 100000.
    Type: Grant
    Filed: April 19, 2011
    Date of Patent: June 9, 2015
    Assignee: Kao Corporation
    Inventors: Haruhiko Doi, Yosuke Uchino, Kazuhiko Nishimoto
  • Patent number: 9048189
    Abstract: Plasma processing methods of a semiconductor manufacturing apparatus which can minimize the amount of impurities adhered to the surface of a wafer, when a desired process using plasma is performed. According to the plasma processing methods of the semiconductor manufacturing apparatus, after the desired process is completed, the plasma generated over the wafer is diffused, and then the wafer is de-chucked.
    Type: Grant
    Filed: March 10, 2011
    Date of Patent: June 2, 2015
    Assignee: SAMSUNG Electronics Co., Ltd.
    Inventors: Hyun-Su Jun, Ki-Sang Kim, Seung-Heong Lee, Jong-Bum Kim, Min-Woung Choi, In-Joong Kim
  • Patent number: 9048066
    Abstract: A method is for etching successive substrates on a platen in an inductively coupled plasma chamber in which the etching process results in carbonaceous deposits in the chamber. The method includes (a) interrupting the etching processing of substrates, (b) running an oxygen or oxygen containing plasma within the chamber and removing gaseous by-products, and (c) resuming the etch processing of substrates. The method is characterized in that it further includes the step of running an argon plasma in the chamber after step (b) with the platen biased.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: June 2, 2015
    Assignee: SPTS TECHNOLOGIES LIMITED
    Inventors: Stephen R Burgess, Alex Theodosiou
  • Patent number: 9039905
    Abstract: A method of forming a lighting system comprises providing a cavity having at least a first array of first optical elements and a second array of second optical elements that have a different shape than the first array, filling the cavity with a curable resin, applying a secondary optical element to the curable resin in alignment with the first optical array, curing the resin to form a cured assembly, and removing the cured assembly from the cavity.
    Type: Grant
    Filed: February 18, 2013
    Date of Patent: May 26, 2015
    Assignee: 3M Innovative Properties Company
    Inventors: Andrew J. Ouderkirk, Erin A. Binder, Nicholas T. Gabriel, Kelly Reed Ingham, Wesley A. Raider, Shrey Gupta, Olester Benson, Jr., Huang Chin Hung
  • Patent number: 9039916
    Abstract: A method for removing copper-oxide from copper powder, the method comprising: providing a copper powder defined by each particle having a copper core and a copper-oxide layer surrounding the copper core; disposing the particles in an etching solution in a container, wherein the etching solution removes the copper-oxide layer from each particle; decanting the etching solution and by-products; washing the particles; disposing the washed particles in an organic solvent; coating each copper core with an organic material from the organic solvent; dispersing the particles in the organic solvent; and providing the copper powder as dispersed copper cores that are absent a copper-oxide layer and have an organic coating, wherein the steps of dispersing in the etching solution, decanting, washing, disposing in the organic solvent, coating, and dispersing are performed in situ with the plurality of particles disposed in liquid, absent any exposure of the copper cores to air.
    Type: Grant
    Filed: December 6, 2010
    Date of Patent: May 26, 2015
    Assignee: SDCmaterials, Inc.
    Inventor: Stephen Edward Lehman, Jr.
  • Patent number: 9029262
    Abstract: A method of forming a contact hole pattern, including: a block copolymer layer forming step in which a layer containing a block copolymer having a plurality of blocks bonded is formed on a substrate having on a surface thereof a thin film with a hole pattern formed, so as to cover the thin film; a phase separation step in which the layer containing the block copolymer is subjected to phase separation; a selective removing step in which phase of at least one block of the plurality of blocks constituting the block copolymer is removed, wherein hole diameter of the hole pattern formed on the thin film is 0.8 to 3.1 times period of the block copolymer, and in the layer forming step, thickness between upper face of the thin film and surface of the layer containing the block copolymer is 70% or less of thickness of the thin film.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: May 12, 2015
    Assignees: Tokyo Ohka Kogyo Co., Ltd., Riken
    Inventors: Takahiro Senzaki, Ken Miyagi, Shigenori Fujikawa
  • Patent number: 9018098
    Abstract: A silicon layer is etched through a patterned mask formed thereon using an etch chamber. A fluorine (F) containing etch gas and a silicon (Si) containing chemical vapor deposition gas are provided in the etch chamber. The fluorine (F) containing etch gas is used to etch features into the silicon layer, and the silicon (Si) containing chemical vapor deposition gas is used to form a silicon-containing deposition layer on sidewalls of the features. A plasma is generated from the etch gas and the chemical vapor deposition gas, and a bias voltage is provided. Features are etched into the silicon layer using the plasma, and a silicon-containing passivation layer is deposited on the sidewalls of the features which are being etched. Silicon in the passivation layer primarily comes from the chemical vapor deposition gas. The etch gas and the chemical vapor deposition gas are then stopped.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: April 28, 2015
    Assignee: Lam Research Corporation
    Inventors: Jaroslaw W. Winniczek, Robert P. Chebi
  • Patent number: 9005461
    Abstract: A plasma monitoring method using a sensor, the sensor having a substrate; a first electrode, the first electrode being a conductive electrode and formed on the substrate while being isolated from the substrate; an insulating film formed on the first electrode; a contact hole formed in the insulating film and having a depth from a surface of the insulating film to the first electrode; and a second electrode, the second electrode being a conductive electrode, formed on the surface of the insulating film, and faced to plasma during a plasma process, the plasma monitoring method including measuring and monitoring potentials of the first electrode and the second electrode or a potential difference between the first electrode and the second electrode during the plasma process is disclosed. A plasma monitoring system carrying out the plasma monitoring method is also disclosed.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: April 14, 2015
    Assignees: Lapis Semiconductor Co., Ltd., Tohoku University
    Inventors: Tomohiko Tatsumi, Seiji Samukawa
  • Patent number: 8999850
    Abstract: Methods and apparatus for etching materials using tetramethylammonium hydroxide (TMAH) are described. The methods may involve including an additive when applying the TMAH to the material to be etched. The additive may be a gas, and in some situations may be clean dry air. The clean dry air may be provided with the TMAH to minimize or prevent the formation of hillocks in the etched structure. Apparatus for performing the methods are also described.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: April 7, 2015
    Assignee: STMicroelectronics Pte Ltd
    Inventors: Ying Yu, Tien Choy Loh, Shian Yeu Kam
  • Patent number: 8992785
    Abstract: A method of etching a material layer on a substrate is described. In one embodiment, the method includes modifying an etch resistance of a material layer to a pre-determined etch process by doping the material layer using energetic charged particles, and etching the modified material layer using the pre-determined etch process.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: March 31, 2015
    Assignee: TEL Epion Inc.
    Inventor: John J. Hautala
  • Patent number: 8986553
    Abstract: A method for manufacturing an optical semiconductor device includes the steps of preparing a substrate product including a semiconductor layer, a mesa structure, and a protective layer; forming a buried layer composed of a resin on the substrate product; forming a first opening in the buried layer on the mesa structure; forming a second opening in the buried layer on the semiconductor layer; exposing the mesa structure and the semiconductor layer by etching the protective layer; forming a first electrode in the first opening; and forming a second electrode in the second opening. The step of forming the second opening includes a first etching step including etching the buried layer using a first resist mask for forming a recess and a second etching step including etching the buried layer using a second resist mask having an opening pattern which has an opening width not smaller than that of the recess.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: March 24, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takamitsu Kitamura, Hideki Yagi
  • Patent number: 8980751
    Abstract: Polymerized material on a substrate may be removed by exposure to vacuum ultraviolet (VUV) radiation from an energy source within a gaseous atmosphere of a controlled composition. Following such removal, additional etching techniques are also described for nano-imprinting.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: March 17, 2015
    Assignees: Canon Nanotechnologies, Inc., Molecular Imprints, Inc.
    Inventors: Gerard M. Schmid, Michael N. Miller, Byung-Jin Choi, Douglas J. Resnick, Sidlgata V. Sreenivasan, Frank Y. Xu, Darren D. Donaldson
  • Patent number: 8916473
    Abstract: An effective chemical mechanical planarization (CMP) method is provided for forming vias in silicon wafers for the fabrication of stacked devices using TSV (through-silicon via) technology. The method affords high removal rates of both metal (e.g., copper) and silicon such that a need for a grinding step prior to CMP processing may not be necessary. The method affords an approximately 1:1 Cu:Si selectivity for removal of silicon and copper under appropriate conditions and the Cu:Si selectivity is tunable by adjustment of levels of some key components.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: December 23, 2014
    Assignee: Air Products and Chemicals, Inc.
    Inventors: James Matthew Henry, Daniel Hernandez Castillo, II
  • Patent number: 8916472
    Abstract: Embodiments described herein provide approaches for interconnect formation in a semiconductor device using a sidewall mask layer. Specifically, a sidewall mask layer is deposited on a hard mask in a merged via region of the semiconductor device following removal of a planarization layer previously formed on the hard mask. The sidewall mask layer is conformally deposited on the hard mask, and acts like a sacrificial layer to protect the hard mask during a subsequent via etch. This reduces the via critical dimension (CD) and reduces the CD elongation along the hard mask line direction during the via etch.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: December 23, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xiang Hu, Mingmei Wang, Liu Huang
  • Patent number: 8906123
    Abstract: A method and associated composition for CMP processing of noble metal-containing substrates (such as ruthenium-containing substrates) afford both high removal rates of the noble metal and are tunable with respect to rate of noble metal removal in relation to removal of other films. Low levels of an oxidizing agent containing one or more peroxy-functional group(s) can be used along with a novel ligand to effectively polish noble metal substrates.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: December 9, 2014
    Assignee: Air Products and Chemicals Inc.
    Inventor: Xiaobo Shi
  • Patent number: 8906807
    Abstract: Fin-defining spacers are formed on an array of mandrel structure. Mask material portions can be directionally deposited on fin-defining spacers located on one side of each mandrel structure, while not deposited on the other side. A photoresist layer is subsequently applied and patterned to form an opening, of which the overlay tolerance increases by a pitch of fin-defining spacers due to the mask material portions. Alternately, a conformal silicon oxide layer can be deposited on fin-defining spacers and structure-damaging ion implantation is performed only on fin-defining spacers located on one side of each mandrel structure. A photoresist layer is subsequently applied and patterned to form an opening, from which a damaged silicon oxide portion and an underlying fin-defining spacer are removed, while undamaged silicon oxide portions are not removed. An array of semiconductor fins including a vacancy can be formed by transferring the pattern into a semiconductor layer.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Marc A. Bergendahl, David V. Horak, Charles W. Koburger, III, Shom Ponoth, Chih-Chao Yang
  • Patent number: 8894872
    Abstract: A liquid etching composition comprising: (a) at least one etching agent precursor having an activation temperature of at least 400° C., at which temperature said precursor yields an active agent suitable for chemical etching of glass, said precursor present at a concentration of at least 2.5% w/w; (b) a binder; and (c) a liquid vehicle.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: November 25, 2014
    Assignee: DIP Tech Ltd.
    Inventors: Matti Ben-Moshe, Michael Kheyfets
  • Patent number: 8889563
    Abstract: An aspect of the invention is to provide a method and apparatus for etching the silicon oxide layer of a semiconductor substrate, whereby the processing time for cleaning or rinsing, as well as any undesired aftereffects by residual hydrofluoric acid, may be reduced, in using the dry etching method involving the use of dense carbon dioxide that contains hydrofluoric acid, during the manufacturing process of a micro-electronic device.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: November 18, 2014
    Assignee: Pukyong National University Industry-University Cooperation Foundation
    Inventor: Kwon-Taek Lim
  • Patent number: 8889021
    Abstract: A sensing device for measuring a plasma process parameter in a plasma chamber for processing workpieces may include a substrate with one or more sensor embedded in the substrate. The substrate can have a surface made of substantially the same material as workpieces that are plasma processed in the plasma chamber. Each sensor can include a collector portion made of substantially the same material as the substrate surface. The collector portion includes a surface that is level with the surface of the substrate. Sensor electronics are embedded into the substrate and coupled to the collector portion. When the substrate surface is exposed to a plasma one or more signals resulting from the plasma can be measured with the sensor(s).
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: November 18, 2014
    Assignee: KLA-Tencor Corporation
    Inventors: Earl Jensen, Mei Sun