Patents Examined by Maliheh Malek
  • Patent number: 10655221
    Abstract: A method for depositing an oxide film on a substrate by thermal ALD and PEALD, includes: providing a substrate in a reaction chamber; depositing a first oxide film on the substrate by thermal ALD in the reaction chamber; and without breaking a vacuum, continuously depositing a second oxide film on the first oxide film by PEALD in the reaction chamber.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: May 19, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Atsuki Fukazawa, Hideaki Fukuda
  • Patent number: 10658399
    Abstract: A transistor includes a semiconductor layer comprising a channel portion, a first contact portion and a second contact portion, a gate electrode facing the floating gate, and a floating gate disposed between the semiconductor layer and the gate electrode, the floating gate being insulated from the semiconductor layer and the gate electrode. The floating gate comprises an oxide semiconductor.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: May 19, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jihun Lim, Jaybum Kim, Joonseok Park, Kyoungseok Son, Junhyung Lim
  • Patent number: 10643906
    Abstract: An embodiment of the invention comprises a method of forming a transistor comprising forming a gate construction having an elevationally-outermost surface of conductive gate material that is lower than an elevationally-outer surface of semiconductor material that is aside and above both sides of the gate construction. Tops of the semiconductor material and the conductive gate material are covered with masking material, two pairs of two opposing sidewall surfaces of the semiconductor material are laterally exposed above both of the sides of the gate construction. After the covering, the semiconductor material that is above both of the sides of the gate construction is subjected to monolayer doping through each of the laterally-exposed two opposing sidewall surfaces of each of the two pairs and forming there-from doped source/drain regions above both of the sides of the gate construction.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: May 5, 2020
    Assignee: Micron Technology, Inc.
    Inventors: David K. Hwang, John A. Smythe, Haitao Liu, Richard J. Hill, Deepak Chandra Pandey
  • Patent number: 10643896
    Abstract: A method for producing a via in a wafer includes providing a wafer, comprising silicon. The method includes producing a conductive region, in the form of a conductor track, preferably composed of polycrystalline silicon, in the wafer. The method includes producing a hole in the wafer such that the hole is fluidically connected to the conductive region and the sidewalls of the hole comprise silicon. The method includes applying a tungsten hexafluoride-resistant protective layer, produced from silicon oxide, in the region of the surface of the hole that is to be produced or has been produced, such that an opening of the hole is free of a protective layer. The method includes applying tungsten hexafluoride to the hole and the region of the opening of the hole by a reducing-agent-free vapor phase deposition process, preferably in the form of a CVD process, for producing the via.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: May 5, 2020
    Assignee: Robert Bosch GmbH
    Inventors: Heiko Stahl, Jochen Reinmuth, Markus Kuhnke, Stefan Majoni, Timo Schary
  • Patent number: 10636757
    Abstract: An integrated circuit package includes a die, a plurality of conductive vias, an alignment mark and an insulating encapsulation. The die includes a plurality of conductive pads. The conductive vias contacts the conductive pads respectively. The alignment mark is disposed on the die and spaced apart from the conductive vias. The insulating encapsulation encapsulates the die and contacts side surfaces of the conductive vias and the alignment mark.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: April 28, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ching-Jung Yang, Ming-Yen Chiu
  • Patent number: 10608060
    Abstract: An organic light-emitting diode display including a substrate, a first transistor, and an organic light-emitting element. The first transistor is positioned on the substrate. The first transistor includes a first active layer including a first source region, a first channel region extending from the first source region, a first drain region extending from the first channel region, a first conductive pattern, and a first gate electrode positioned on the first active layer. The organic light-emitting element is connected to the first transistor. The first conductive pattern is in contact with the first active layer and covers the first source region and the second source region.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: March 31, 2020
    Inventors: Duk-Sung Kim, Byung Seon An
  • Patent number: 10600642
    Abstract: There is provided a technique which includes: forming a film containing at least Si, O and N on a substrate in a process chamber by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: forming a first layer by supplying a precursor gas containing at least a Si—N bond and a Si—Cl bond and a first catalyst gas to the substrate; exhausting the precursor gas and the first catalyst gas in the process chamber through an exhaust system; forming a second layer by supplying an oxidizing gas and a second catalyst gas to the substrate to modify the first layer; and exhausting the oxidizing gas and the second catalyst gas in the process chamber through the exhaust system.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: March 24, 2020
    Assignee: Kokusai Electric Corporation
    Inventors: Yoshiro Hirose, Yoshitomo Hashimoto
  • Patent number: 10586713
    Abstract: Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming a plurality of fins on a surface of the semiconductor substrate; forming an isolation flowable layer covering the plurality of fins over the semiconductor substrate; performing a first annealing process to turn the isolation flowable layer into an isolation film; and forming first well regions and second well regions in the fins and the semiconductor substrate. The second well regions are at two sides of the first well regions and contact with the first well regions; the first well regions have a first type of well ions; the second well regions have a second type of well ions; and the first type is opposite to the second type in the conductivities.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: March 10, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Fei Zhou
  • Patent number: 10580645
    Abstract: Methods for forming silicon nitride films are provided. In some embodiments, silicon nitride can be deposited by atomic layer deposition (ALD), such as plasma enhanced ALD. One or more silicon nitride deposition cycle comprise a sequential plasma pretreatment phase in which the substrate is sequentially exposed to a hydrogen plasma and then to a nitrogen plasma in the absence of hydrogen plasma, and a deposition phase in which the substrate is exposed to a silicon precursor. In some embodiments a silicon hydrohalide precursors is used for depositing the silicon nitride. The silicon nitride films may have a high side-wall conformality and in some embodiments the silicon nitride film may be thicker at the bottom of the sidewall than at the top of the sidewall in a trench structure. In gap fill processes, the silicon nitride deposition processes can reduce or eliminate voids and seams.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: March 3, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Shinya Ueda, Taishi Ebisudani, Toshiya Suzuki
  • Patent number: 10573738
    Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: February 25, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shang-Hui Tu, Chih-Jen Huang, Jui-Chun Chang, Shin-Cheng Lin, Yu-Hao Ho, Wen-Hsin Lin
  • Patent number: 10566281
    Abstract: Some embodiments include methods of forming integrated assemblies. First conductive structures are formed within an insulative support material and are spaced along a first pitch. Upper regions of the first conductive structures are removed to form first openings extending through the insulative support material and over lower regions of the first conductive structures. Outer lateral peripheries of the first openings are lined with spacer material. The spacer material is configured as tubes having second openings extending therethrough to the lower regions of the first conductive structures. Conductive interconnects are formed within the tubes. Second conductive structures are formed over the spacer material and the conductive interconnects. The second conductive structures are spaced along a second pitch, with the second pitch being less than the first pitch. Some embodiments include integrated assemblies.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: February 18, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 10559660
    Abstract: A semiconductor device includes a semiconductor layer, a metal layer electrically contacting the semiconductor layer, and a two-dimensional material layer between the semiconductor layer and the metal layer and having a two-dimensional crystal structure.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: February 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Minhyun Lee, Haeryong Kim, Hyeonjin Shin, Seunggeol Nam, Seongjun Park
  • Patent number: 10559519
    Abstract: The present disclosure relates to semiconductors. Some embodiments may include a series circuit arrangement of power semiconductors comprising: cooling-water boxes arranged on the semiconductors and electrically connected to them; two cooling-water distributor lines; respective branchings on the cooling-water distributor lines for the cooling chambers; and a control electrode arranged on the cooling-water distributor lines. The cooling chambers are connected in parallel between the cooling-water distributor lines with respect to a cooling-water stream. The cooling chambers are connected to the branchings via a respective connecting line. For at least some of the cooling chambers, the branchings on the cooling-water distributor lines are arrayed relative to the position of the respective cooling chamber in offset manner in relation to a geometrically shortest possible link to the cooling-water distributor lines, so that a difference of potential between the cooling chambers and the branchings is minimized.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: February 11, 2020
    Inventors: Johann Holweg, Katrin Benkert, Harald Landes, André Leonide
  • Patent number: 10559715
    Abstract: A light emitting diode is provided to comprises: a substrate that has an elongated rectangular shape in one direction; a light emitting structure positioned on the substrate and having an opening for exposing a first conductive semiconductor layer; a first electrode pad disposed to be closer to a first corner of the substrate; a second electrode pad disposed to be relatively closer to a second corner of the substrate opposing to the first corner; a first extension extending from the first electrode pad; and a second extension and a third extension extending from the second electrode pad to sides of the first extension, wherein an imaginary line connecting an end of the second extension and an end of the third extension is located between the first electrode pad and the first corner.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: February 11, 2020
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Mae Yi Kim, Jin Woong Lee, Yeo Jin Yoon, Seom Geun Lee, Yong Woo Ryu, Keum Ju Lee
  • Patent number: 10553633
    Abstract: A photodetector includes a two-terminal bipolar phototransistor arranged on a substrate. The phototransistor includes a base, a collector, and an emitter. An electrical connection is made between the base and the local substrate near a region of the phototransistor. The electrical connection can be by way of metal interconnects.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: February 4, 2020
    Assignees: Wispro Technology Cosulting Corporation Limited
    Inventors: Klaus Y. J. Hsu, Brett W. C. Liao
  • Patent number: 10551165
    Abstract: This present disclosure generally relates to devices, methods, and systems for producing large numbers of SiO2 coated silicon chips with uniform film thickness controlled to angstrom and sub angstrom levels. The disclosure further relates to etching plates configured for receiving a plurality of chips mounted thereon.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: February 4, 2020
    Inventors: Christopher C. Striemer, Jared A. Carter, Wade Campney
  • Patent number: 10529624
    Abstract: Semiconductor devices and methods are provided to fabricate FET devices having overlapping gate and source/drain contacts while preventing electrical shorts between the overlapping gate and source/drain contacts. For example, a semiconductor device includes a plurality of semiconductor fins patterned in a starting semiconductor substrate; a set of gate structures formed on the starting semiconductor substrate; a set of spacers formed around each of the set of gate structures; a source and drain region grown around the plurality of fins; a conductive metal material on the source and drain region, an insulating material is configured to be deposited over an upper surface of the conductive metal material and the gate structure; and a plurality of contacts in the insulator material. The plurality of contacts is formed such that a bottom surface of the plurality of contacts is in contact with at least a portion of the upper surface of the gate structure.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10522549
    Abstract: Provided herein are approaches for forming a gate dielectric layer for a DRAM device, the method including providing a substrate having a recess formed therein, the recess including a sidewall surface and a bottom surface. The method may further include performing an ion implant into just the bottom surface of the recess, and forming a gate dielectric layer along the bottom surface of the recess and along the sidewall surface of the recess. Once formed, a thickness of the gate dielectric layer along the sidewall surface is approximately the same as a thickness of the gate dielectric layer along the bottom surface of the recess. In some embodiments, the gate dielectric layer is thermally grown within the recess. In some embodiments, the ion implant is performed after a mask layer atop the substrate is removed.
    Type: Grant
    Filed: February 17, 2018
    Date of Patent: December 31, 2019
    Inventors: Baonian Guo, Qintao Zhang
  • Patent number: 10504821
    Abstract: A TSV structure includes a substrate comprising at least a TSV opening formed therein, a conductive layer disposed in the TSV opening, and a bi-layered liner disposed in between the substrate and the conductive layer. More important, the bi-layered liner includes a first liner and a second liner, and a Young's modulus of the first liner is different from a Young's modulus of the second liner.
    Type: Grant
    Filed: January 29, 2016
    Date of Patent: December 10, 2019
    Inventors: Chu-Fu Lin, Ming-Tse Lin, Kuei-Sheng Wu
  • Patent number: 10486263
    Abstract: Provided is a semiconductor device formed by performing bonding at room temperature with respect to a wafer in which bonded electrodes and insulating layers and are respectively exposed to front surfaces, including a bonding interlayer which independently exhibits non-conductivity and exhibits conductivity by being bonded to the bonded electrodes, between the front surfaces.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: November 26, 2019
    Inventors: Jun Utsumi, Takayuki Goto, Takenori Suzuki, Kensuke Ide