Abstract: Radio frequency motion sensors may be configured for operation in a common vicinity so as to reduce interference. In some versions, interference may be reduced by timing and/or frequency synchronization. In some versions, a master radio frequency motion sensor may transmit a first radio frequency (RF) signal. A slave radio frequency motion sensor may determine a second radio frequency signal which minimizes interference with the first RF frequency. In some versions, interference may be reduced with additional transmission adjustments such as pulse width reduction or frequency and/or timing dithering differences. In some versions, apparatus may be configured with multiple sensors in a configuration to emit the radio frequency signals in different directions to mitigate interference between emitted pulses from the radio frequency motion sensors.

Abstract: A hybrid bonding structure includes a first conductive structure and a second conductive structure. The first conductive structure includes a first conductive layer. A first barrier surrounds the first conductive layer. A first air gap surrounds and contacts the first barrier. A first dielectric layer surrounds and contacts the first air gap. The second conductive structure includes a second conductive layer. A second barrier contacts the second conductive layer. A second dielectric layer surrounds the second barrier. The second conductive layer bonds to the first conductive layer. The first dielectric layer bonds to the second dielectric layer.

Abstract: A radar system includes a transmitter including a power amplifier (PA) for amplifying a local oscillator (LO) signal, to generate an amplified signal. The radar system also includes a receiver including an IQ generator for generating an I signal based on the LO signal and for generating a Q signal based on the LO signal and a low noise amplifier (LNA) for amplifying a looped back signal, to generate a receiver signal. The receiver also includes a first mixer for mixing the receiver signal and the I signal, to generate a baseband I signal and a second mixer for mixing the receiver signal and the Q signal, to generate a baseband Q signal. Additionally, the radar system includes a waveguide loopback for guiding the amplified signal from the transmitter to the receiver as the looped back signal.

Abstract: The present application discloses a semiconductor device with stacked dies and the method for fabricating the semiconductor device with the stacked dies. The semiconductor device includes a first semiconductor die including a first substrate including a first and a second region, a first circuit layer on the first substrate, a control circuit on the first region and in the first circuit layer; and through die vias along the first circuit layer and the second region; a second semiconductor die stacked on the first semiconductor die and including second conductive pads connected to the through die vias and the control circuit; and a third semiconductor die stacked under the first semiconductor die and including third conductive pads connected to the through die vias and the control circuit. The through die vias, the second conductive pads, and the third conductive pads configure transmission channels through which the control circuit is capable to access the second and the third semiconductor die.

Abstract: A thin-film storage transistor includes (a) first and second semiconductor regions comprising polysilicon of a first conductivity; and (b) a channel region between the first and second semiconductor regions, the channel region comprising single-crystal epitaxial grown silicon, and wherein the thin-film storage transistor is formed above a monocrystalline semiconductor substrate.

Abstract: A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

Abstract: An IC chip includes I/O bumps on a back side, a first die, a second die, a first circuit, and a second circuit. The first die has driver circuits for LED devices, the LED devices being located on a front-facing surface of the first die. The first circuit extends from the front side toward the back side and across a thickness of the first die. The first circuit provides electrical connections between the LED devices and at least some of the I/O bumps. The first die and the second die can be stacked vertically or arranged laterally adjacent. The second circuit extends between the first die and the second die to electrically connect the first die and the second die. A circuit board can be electrically connected to the IC chip through the I/O bumps to, among other things, provide power to the various components of the IC chip.

Abstract: A semiconductor device includes a first electrode on a semiconductor element at a first location and a second electrode on the semiconductor element at a second location spaced from the first location. And insulating film covers the first electrode, the second electrode and a third electrode. First and second pads are on the insulating film. The first electrode contacts the first pad through an opening in a first portion of the insulating film. The second electrode contacts the second pad each through an opening in a second portion of the insulating film. A bonding surface of the first pad is at a first distance above one portion of the insulating film, and a second distance above another. A bonding surface of the second pad likewise at different distances above the insulating film depending on location.

Abstract: A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first semiconductor device, a second semiconductor device, and an alignment material. The first semiconductor device has a first bonding layer, and the first bonding layer includes a first bond pad contacting an organic dielectric material. The second semiconductor device has a second bonding layer, and the second bonding layer includes a second bond pad contacting the organic dielectric material. The alignment material is between the first bonding layer and the second bonding layer.

Abstract: A semiconductor device includes a first structure including a first bonding structure, and a second structure on the first structure and including a second bonding structure connected to the first bonding structure. The first bonding structure includes a first insulating layer, a first bonding insulating layer on the first insulating layer, first bonding pads penetrating at least a portion of the first insulating layer and the first bonding insulating layer, and first metal patterns in the first insulating layer and in contact with the first bonding insulating layer, and having an upper surface at a lower level than upper surfaces of the first bonding pads. The second bonding structure includes a second bonding insulating layer bonded to the first bonding insulating layer, a second insulating layer on the second bonding insulating layer, and second bonding pads penetrating the second bonding insulating layer and connected to the first bonding pads.

Abstract: A display device includes a first substrate having a display area and a peripheral area, the first substrate including a first inclined surface disposed at an outer portion of the peripheral area and being angled relative to the first substrate in the display area; a pixel structure disposed on the first substrate in the display area; a second substrate disposed on the pixel structure; a first electrode disposed on the first inclined surface and between the first substrate and the second substrate; and a second electrode disposed on sides of the first and second substrates, the second electrode being in contact with the first electrode.

Abstract: An electronic device includes a support substrate to which a first electronic chip and a second electronic chip are mounted in a position situated on top of one another. First electrical connection elements are interposed between the first electronic chip and the support substrate. Second electrical connection elements are interposed between the second electronic chip and the support substrate and are situated at a distance from a periphery of the first electronic chip. Third electrical connection elements are interposed between the first electronic chip and the second electronic chip.

Abstract: The subject application discloses a substrate. The substrate includes a first conductive layer, a first bonding layer, a first dielectric layer, and a conductive via. The first bonding layer is disposed on the first conductive layer. The first dielectric layer is disposed on the first bonding layer. The conductive via penetrates the first dielectric layer and is electrically connected with the first conductive layer.

Abstract: A method of manufacturing an electronic device is provided, wherein the method includes the following steps. A first substrate is provided, wherein the first substrate has a top surface and a side surface. A first wire is formed on the top surface of the first substrate. An auxiliary bonding pad is formed on the top surface of the first substrate, and the auxiliary bonding pad contacts the first wire. A second wire is formed on the side surface of the first substrate, and the second wire contacts the auxiliary bonding pad. The second wire and the auxiliary bonding pad include at least one same material.

Abstract: An objective of the disclosure is to provide an organic light-emitting composite material based on an exciplex, which, when used as a light-emitting layer, can enhance the efficiency of an organic electroluminescent device. The disclosure also relates to an organic light-emitting device comprising the organic light-emitting composite material, and use of the organic light-emitting composite material of the disclosure for an organic electron device.

Abstract: A connection electrode includes a first metal film, a second metal film, a mixed layer, and an extraction electrode. The second metal film is located on the first metal film, and the extraction electrode is located on the second metal film. The mixed layer includes a mix of metal particles of the first and second metal films. As viewed in a first direction in which the first metal film and the second metal film are on top of each other, at least a portion of the mixed layer is in a first region that overlaps a bonding plane between the extraction electrode and the second metal film.

Abstract: A semiconductor device includes a semiconductor chip and a package. The semiconductor chip includes a signal processing circuit, a plurality of pads, and a first resistor which arc formed on a semiconductor substrate. On the semiconductor chip, there is no shot-circuiting between a first pad and a second pad of the plurality of pads. A signal input terminal of the signal processing circuit is connected to the second pad. The first resistor is provided between a reference potential supply terminal for supplying a power supply potential and the first pad. A specific terminal of the plurality of terminals of the package is connected to the first pad by a first bonding wire, and is connected to the second pad by a second bonding wire.

Abstract: A semiconductor chip includes a body portion with a front surface and a rear surface; a through electrode penetrating the body portion; a wiring portion that is disposed over the front surface of the body portion; a rear connection electrode that is disposed over the rear surface of the body portion; and a front connection electrode that is disposed over the wiring portion, wherein the rear connection electrode includes a power rear connection electrode that is simultaneously connected to two or more power through electrodes, and wherein a width of the power rear connection electrode is greater than a width of the front connection electrode.