Abstract: A package has a first region and a second region surrounded by the first region. The package includes a first die, a second die, an encapsulant, and an inductor. The first die extends from the first region to the second region. The second die is bonded to the first die and is located within a span of the first die. The encapsulant is aside the second die. At least a portion of the encapsulant is located in the second region. The inductor is located in the second region. The inductor laterally has an offset from the second die. A metal density in the first region is greater than a metal density in the second region.

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes one or a plurality of chips on a substrate, bumps disposed below each of the one or plurality of chips, an underfill material layer on the substrate, on a side surface of each of the bumps, and extending to side surfaces of the one or plurality of chips, and a mold layer on the substrate and contacting the underfill material layer. The underfill material layer includes a first side portion, a second side portion on the first side portion and having a slope, steeper than a slope of the first side portion, and a third side portion on the second side portion and having a slope that is less steep than a slope of the second side portion.

Abstract: A chip-stacked semiconductor package includes: a base chip having a base through via; a first chip stacked on the base chip in an offset form, wherein the first chip has a first exposed surface and a first through via electrically connected to the base through via; a first molding layer positioned on the base chip and covering a first non-exposed surface, facing the first exposed surface, of the first chip; a second chip stacked on the first chip in an offset form, wherein the second chip has a second exposed surface and a second through via electrically connected to the first through via; and a second molding layer formed on the first chip and covering a second non-exposed surface, facing the second exposed surface, of the second chip.

Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

Abstract: A package includes a first die that includes a first metallization layer, one or more first bond pad vias on the first metallization layer, wherein a first barrier layer extends across the first metallization layer between each first bond pad via and the first metallization layer, and one or more first bond pads on the one or more first bond pad vias, wherein a second barrier layer extends across each first bond pad via between a first bond pad and the first bond pad via, and a second die including one or more second bond pads, wherein a second bond pad is bonded to a first bond pad of the first die.

Abstract: A package substrate may include an insulation substrate, at least one redistribution layer (RDL) and a redistribution pad. The RDL may be included in the insulation substrate. The redistribution pad may extend from the RDL. The redistribution pad may include at least one segmenting groove in a radial direction of the redistribution pad. Thus, the at least one segmenting groove in the radial direction of the redistribution pad may reduce an area of the redistribution pad. Therefore, application of physical stress to a PID disposed over the redistribution pad may be suppressed, and thus generation of cracks in the PID may be reduced. Further, spreading of the cracks toward the redistribution pad from the PID may also be suppressed, and thus reliability the semiconductor package may be improved.

Abstract: A through-silicon via (TSV) key for overlay measurement includes: a first TSV extending through at least a portion of a substrate in a first direction that is perpendicular to a top surface of the substrate; and at least one ring pattern, which is apart from and surrounds the first TSV in a second direction that is parallel to the top surface of the substrate, the at least one ring pattern being arranged in a layer that is lower than a top surface of the first TSV in the first direction, wherein an inner measurement point corresponds to the first TSV, an outer measurement point corresponds to the at least one ring pattern, and the inner measurement point and the outer measurement point are arranged to provide an overlay measurement of a TSV.

Abstract: A semiconductor package for high-speed die connections using a conductive insert, the semiconductor package comprising: a die; a plurality of redistribution layers; a conductive insert housed in a perforation through the plurality of redistribution layers; and a conductive bump conductively coupled to an input/output (I/O) connection point of the die via the conductive insert.

Abstract: Layouts for pads and conductive lines of memory devices are disclosed. A memory device may include memory cells and conductive lines arranged above memory cells. The conductive lines may extend from substantially a first side of the memory device to substantially a second side of the memory device. Each of the conductive lines may be electrically coupled to a bond pad, a first probe pad and a second probe pad. The bond pad may be positioned at or near the first side and be configured to receive power. The first probe pad may be positioned at or near the first side and be configured to be electrically coupled to a probe. The second probe pad may be positioned at or near the second side. Associated systems and methods are also disclosed.

Abstract: A semiconductor package includes a base substrate, a first semiconductor chip on the base substrate, a dam structure on the base substrate and surrounding the first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a non-conductive film, and a molding member. The non-conductive film may be between the base substrate, the first semiconductor chip, and the second semiconductor chip. The molding member may cover the base substrate, the first semiconductor chip, and the second semiconductor chip. A level of an upper surface of the first semiconductor chip and a level of an upper surface of the dam structure may be at a same level.

Abstract: A semiconductor package includes a first semiconductor die, a second semiconductor die and a plurality of bumps. The first semiconductor die has a front side and a backside opposite to each other. The second semiconductor die is disposed at the backside of the first semiconductor die and electrically connected to first semiconductor die. The plurality of bumps is disposed at the front side of the first semiconductor die and physically connects first die pads of the first semiconductor die. A total width of the first semiconductor die may be less than a total width of the second semiconductor die.

Abstract: A chip package is provided. The chip package may include at least one chip, an exposed metal region and a metal protection layer structure over the exposed metal region and configured to protect the metal region from oxidation. The protection layer structure includes a low-temperature deposited oxide, and a hydrothermally converted metal oxide layer over the protection layer structure.

Abstract: A semiconductor package includes a redistribution structure including an insulating layer having an upper surface and a lower surface, a redistribution pad and a redistribution pattern on the lower surface of the insulating layer and electrically connected to each other, and a passivation layer on the lower surface of the insulating layer and having an opening exposing at least a portion of the redistribution pad; a semiconductor chip on the redistribution structure and including a connection pad electrically connected to the redistribution pad; an encapsulant on the redistribution structure and encapsulating the semiconductor chip; and a connection bump and a dummy bump on the passivation layer, wherein the redistribution pattern has a width narrower than a width of the redistribution pad, the connection bump vertically overlaps the redistribution pad, and the dummy bump vertically overlaps the redistribution pattern.

Abstract: A bonded structure is disclosed. The bonded structure can include a semiconductor element comprising active circuitry. The bonded structure can include an obstructive element bonded to the semiconductor element along a bond interface, the obstructive element including an obstructive material disposed over the active circuitry, the obstructive material configured to obstruct external access to the active circuitry. The bonded element can include an artifact structure indicative of a wafer-level bond in which the semiconductor element and the obstructive element formed part of respective wafers directly bonded prior to singulation.

Abstract: One aspect provides a method, including: obtaining sensor data from a ground penetrating radar (GPR) unit; analyzing, using a processor, the sensor data to detect a first object and a second object, the second object being associated with the first object based on location; identifying, with the processor, an underground pipe feature based on the analyzing; associating a position of the underground pipe feature with a location in a pipe network; selecting a subset of the pipe network including a pipe segment associated with the position of the underground pipe feature; and providing the subset of the pipe network as displayable data to a display device. Other aspects are described and claimed.

Abstract: A memory system includes a memory stack including a number of memory dies interconnected via copper bonding, a logic die coupled to the memory stack via a copper bonding. The memory system further includes a buffer die extended to provide the copper bonding between the logic die and the memory stack and a silicon carrier layer bonded to the memory stack and the logic die.

Abstract: A device structure, along with methods of forming such, are described. The device structure includes a structure, a first passivation layer disposed on the structure, a buffer layer disposed on the first passivation layer, a barrier layer disposed on a first portion of the buffer layer, a redistribution layer disposed over the barrier layer, an adhesion layer disposed on the barrier layer and on side surfaces of the redistribution layer, and a second passivation layer disposed on a second portion of the buffer layer. The second passivation layer is in contact with the barrier layer, the adhesion layer, and the redistribution layer.

Abstract: An interconnection structure of a system on wafer and a PCB based on a TSV process and a method for manufacturing the same. The structure comprises a bottom structural part and a top structural part, the upper surface of the bottom structural part is provided with a plurality of positioning holes; the lower surface of the top structural part is provided with positioning pins; the upper surface of the bottom structural part is provided with a bottom groove, and a system on wafer is arranged in the bottom groove; the lower surface of the system on wafer is connected with the bottom groove; the lower surface of the top structural part is provided with a top groove, and a PCB preformed die is connected in the top groove, and the other end of the PCB preformed die is connected with the system on wafer by an elastic connector.

Abstract: A semiconductor package is provided. The semiconductor package may include a first semiconductor die, a second semiconductor die stacked on the first semiconductor die, the second semiconductor die having a width smaller than a width of the first semiconductor die, a third semiconductor die stacked on the second semiconductor die, the third semiconductor die having a width smaller than the width of the first semiconductor die, and a mold layer covering side surfaces of the second and third semiconductor dies and a top surface of the first semiconductor die. The second semiconductor die may include a second through via, and the third semiconductor die may include a third conductive pad in contact with the second through via.

Abstract: A chip package structure includes a chip stack and a redistribution layer. The chip stack includes multiple chips stacked together, a molding layer encapsulating the multiple chips, and a vertical conductive element extending from a surface of the molding layer reach and coupled to the bonding pad. Each of the multiple chips includes a bonding pad not covered by the multiple chips. The redistribution layer is above the molding layer and includes a conductive layer coupled to the vertical conductive element, and an insulating layer over and partially exposing the conductive layer.