Patents Examined by Marc Armand
  • Patent number: 10256325
    Abstract: According to an embodiment, a method of forming a power semiconductor device is provided. The method includes providing a semiconductor substrate and forming an epitaxial layer on the semiconductor substrate. The epitaxial layer includes a body region, a source region, and a drift region. The method further includes forming a dielectric layer on the epitaxial layer. The dielectric layer is formed thicker above a drift region of the epitaxial layer than above at least part of the body region and the dielectric layer is formed at a temperature less than 950° C.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: April 9, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Stefan Gamerith, Markus Schmitt, Winfried Kaindl, Gerald Sölkner
  • Patent number: 10256156
    Abstract: Vertical field effect transistors (FETs) with minimum pitch and methods of manufacture are disclosed. The structure includes at least one vertical fin structure and gate material contacting with the at least one vertical fin structure. The structure further includes metal material in electrical contact with the ends of the at least one vertical fin.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 10249673
    Abstract: A microelectronic unit includes a semiconductor element having a front surface to which a packaging layer is attached, and a rear surface remote from the front surface. The element includes a light detector including a plurality of light detector element arranged in an array disposed adjacent to the front surface and arranged to receive light through the rear surface. The semiconductor element also includes an electrically conductive contact at the front surface connected to the light detector. The conductive contact includes a thin region and a thicker region which is thicker than the thin region. A conductive interconnect extends through the packaging layer to the thin region of the conductive contact, and a portion of the conductive interconnect is exposed at a surface of the microelectronic unit.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: April 2, 2019
    Assignee: Invensas Corporation
    Inventors: Giles Humpston, Moshe Kriman
  • Patent number: 10243055
    Abstract: Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack that includes a bottom layer, a middle layer, and a top layer is formed over the at least one semiconductor fin in the first region. A second work function stack that includes a first layer and a second layer is formed over the at least one semiconductor fin in the second region. The first layer is continuous with the bottom layer of the first work function stack and the second layer is continuous with the middle layer of the first work function stack but has a smaller thickness than the middle layer. A continuous gate is formed over the first and the second work function stack.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Vijay Narayanan
  • Patent number: 10242980
    Abstract: A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Henry K. Utomo, Kangguo Cheng, Ramachandra Divakaruni, Ravikumar Ramachandran, Huiling Shang, Reinaldo A. Vega
  • Patent number: 10229981
    Abstract: Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Abhijit Jayant Pethe, Tahir Ghani, Harry Gomez
  • Patent number: 10229979
    Abstract: A structure includes a laterally diffused (LD) MOSFET with an n-type drift region disposed on a surface of a substrate and a p-type body region contained in the drift region. The structure further includes an n-type source region contained in the p-type body region; an n-type drain region contained in the n-type drift region; a gate electrode disposed on a gate dielectric overlying a portion of the p-type body region and the n-type drift region and an electrically conductive field shield member disposed within the n-type drift region at least partially beneath the p-type body region and generally parallel to the gate electrode. The electrically conductive buried field shield member is contained within and surrounded by a layer of buried field shield oxide and is common to both a first LD MOSFET and a second LD MOSFET that are connected in parallel. Methods to fabricate the structure are also disclosed.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: March 12, 2019
    Assignee: International Business Machines Corporation
    Inventor: Tak H. Ning
  • Patent number: 10222272
    Abstract: In one embodiment, a semiconductor device (20) includes a semiconductor chip (200) in which functional blocks (201, 202, 203 etc.) and a temperature sensor (208) are integrated. In this embodiment, in response to a change in an operation state of the semiconductor device (20), the on-chip temperature sensor (208) operates to switch from a continuous operation in which it continuously measures a chip temperature to an intermittent operation in which it intermittently measures the chip temperature, or to change a time interval between intermittent measurements of the chip temperature.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: March 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Chiaki Kumahara, Akira Tsurugasaki
  • Patent number: 10224370
    Abstract: A resistive switching device. The device includes a first electrode comprising a first metal material overlying the first dielectric material and a switching material comprising an amorphous silicon material. The device includes a second electrode comprising at least a second metal material. In a specific embodiment, the device includes a buffer material disposed between the first electrode and the switching material. The buffer material provides a blocking region between the switching material and the first electrode so that the blocking region is substantially free from metal particles from the second metal material when a first voltage is applied to the second electrode.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: March 5, 2019
    Assignee: CROSSBAR, INC.
    Inventors: Sung Hyun Jo, Wei Lu
  • Patent number: 10218346
    Abstract: Large area, high current, lateral GaN power transistors are implemented using an on-chip interconnect topology wherein the transistor is arranged as an array of sections, each section comprising a set of transistor islands; gate and source buses that form each gate drive loop have substantially the same track widths; the source bus runs over or under the gate bus, and the tracks are inductively coupled to provide flux cancellation in the gate drive loop, thereby reducing parasitic inductances. The gate delay in each gate drive loop is reduced, minimizing the gate drive phase difference across the transistor. An overlying current redistribution layer preferably has a track width no greater than that of the underlying source and drain buses, for efficient coupling. This topology provides improved scalability, enabling fabrication of multi-section, large scale, high current lateral GaN transistors with reduced gate drive loop inductance, for improved operational stability.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: February 26, 2019
    Assignee: GaN Systems Inc.
    Inventors: Ahmad Mizan, Greg P. Klowak, Xiaodong Cui
  • Patent number: 10217889
    Abstract: An avalanche photodiode device operated in Geiger-mode, the device comprising a P-N junction formed on a substrate with a first semiconductor region and a second semiconductor region with an anode and cathode. The device further comprising a third semiconductor region, the third semiconductor region in physical contact with the second region, not in physical contact with the first region, and being the same semiconductor-type as the first semiconductor region. Additionally comprising a diode on the second semiconductor region and having a turn-on voltage than the P-N junction.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: February 26, 2019
    Assignee: LadarSystems, Inc.
    Inventors: Vinit Dhulla, Drake Miller, Leonard Forbes
  • Patent number: 10217832
    Abstract: A semiconductor device is provided that includes a semiconductor substrate; an insulating film that is provided on the semiconductor substrate, has an opening through which the semiconductor substrate is exposed, and contains oxygen; a first barrier metal portion that is provided at least on a bottom portion of the opening and in which one or more kinds of films are laminated; and an upper electrode provided above the insulating film. The barrier metal is not provided between an upper surface of the insulating film and the upper electrode, or the semiconductor device further comprises a second barrier metal portion between the upper surface of the insulating film and the upper electrode, the second barrier metal portion having a configuration different from that of the first barrier metal portion.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: February 26, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yanzheng Zhang
  • Patent number: 10217859
    Abstract: A semiconductor device is provided that includes a semiconductor substrate; an insulating film that is provided on the semiconductor substrate, has an opening through which the semiconductor substrate is exposed, and contains oxygen; a first barrier metal portion that is provided at least on a bottom portion of the opening and in which one or more kinds of films are laminated; and an upper electrode provided above the insulating film. The barrier metal is not provided between an upper surface of the insulating film and the upper electrode, or the semiconductor device further comprises a second barrier metal portion between the upper surface of the insulating film and the upper electrode, the second barrier metal portion having a configuration different from that of the first barrier metal portion.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: February 26, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yanzheng Zhang
  • Patent number: 10217857
    Abstract: A super junction MOSFET includes a substrate having a first conductive type, an epitaxial layer formed on the substrate, a set of pillars extending from the substrate through the epitaxial layer, the set of pillars being spaced apart from each other, a set of first wells, the set of first wells formed in the epitaxial layer to extend to an upper face of the epitaxial layer, and each of the set of first wells connected to at least one corresponding pillar of the set of pillars, a set of second wells of the first conductive type formed in the set of first wells, and a plurality of gate structures formed on the epitaxial layer, each extending in a first direction to have a stripe shape such that the gate structures are spaced apart from each other. Thus, the gate structure has a relatively small area to reduce an input capacitance of the super junction MOSFET.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: February 26, 2019
    Assignee: DB Hitek Co., Ltd
    Inventors: Young Seok Kim, Bum Seok Kim
  • Patent number: 10211222
    Abstract: A memory device includes a conductive layer, a first electrode over the conductive layer, and a second electrode between the conductive layer and the first electrode. The second electrode is a material different from that of the first electrode. A semiconductor pillar extends through the first and second electrodes, and has an end connected to the conductive layer. A first insulating film is between the semiconductor pillar and the first and second electrodes and between at least a portion of the semiconductor pillar and the conductive layer. A second insulating film is between the conductive layer and the first insulating film. A third insulating film is between the first insulating film and the second electrode, and between the second and third insulating film. The second electrode and conductive layer include a first element and the second and third insulating films comprise an oxide or nitride of the first element.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: February 19, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Takaya Yamanaka
  • Patent number: 10211064
    Abstract: A metal oxide semiconductor field effect transistors (MOSFET) memory array, including a complementary metal oxide semiconductor (CMOS) cell including an n-type MOSFET having a modified gate dielectric; and an n-type or p-type MOSFET having an unmodified gate dielectric layer, where the modified gate dielectric layer incorporates an oxygen scavenging species.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Eduard A. Cartier, Chandrasekharan Kothandaraman
  • Patent number: 10211160
    Abstract: A microelectronic assembly can be made by forming a redistribution structure supported on a carrier, the structure including two or more layers of deposited dielectric material and two or more electrically conductive layers and including conductive features such as pads and traces electrically interconnected by vias. Electrical connectors may project above a second surface of the structure opposite an interconnection surface of the redistribution structure adjacent to the carrier. A microelectronic element may be attached and electrically connected with conductive features at the second surface, and a dielectric encapsulation can be formed contacting the second surface and surfaces of the microelectronic element. Electrically conductive features at the interconnection surface can be configured for connection with corresponding features of a first external component, and the electrical connectors can be configured for connection with corresponding features of a second external component.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: February 19, 2019
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Wael Zohni, Cyprian Emeka Uzoh
  • Patent number: 10211328
    Abstract: A normally-off, heterojunction field effect transistor includes an intrinsic cubic-phase gallium nitride (c-GaN) substrate and an aluminum gallium nitride (AlGaN) capping layer disposed on the intrinsic c-GaN substrate. The AlGaN capping layer includes a first sublayer of intrinsic c-phase AlxGa1-xN disposed on the c-GaN substrate, wherein the first sublayer is of a first thickness; a second sublayer of doped c-phase AlxGa1-xN disposed on the first sublayer, and wherein the second sublayer is of a second thickness and is doped with a dopant. An insulating layer is disposed on the AlGaN capping layer, wherein the insulating layer is of a fourth thickness. A source electrode, a drain electrode, and a gate electrode are positioned adjacent to and on top of the insulating layer, respectively.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: February 19, 2019
    Assignee: Board of Trustees of the University of Illinois
    Inventors: Can Bayram, Ryan William Grady, Kihoon Park
  • Patent number: 10211307
    Abstract: In accordance with an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first cover layer is formed over the sacrificial gate structure, and a second cover layer is formed over the first cover layer. A source/drain epitaxial layer is formed. After the source/drain epitaxial layer is formed, the second cover layer is removed, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed. Part of the first semiconductor layers is removed in the gap, thereby forming spaces between the second semiconductor layers. The spaces are filled with a first insulating material.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: February 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Ching-Wei Tsai, Kuan-Lun Cheng
  • Patent number: 10211315
    Abstract: Structures for a vertical-transport field-effect transistor and methods for forming a structure for a vertical-transport field-effect transistor. A semiconductor fin is formed on a source/drain region. A gate stack is deposited that coats the semiconductor fin and a contact landing area of the source/drain region adjacent to the semiconductor fin. The gate stack is patterned to remove the gate stack from the contact landing area and to form a gate electrode having a section adjacent to the contact landing area. The section of the gate electrode is laterally recessed to form a cavity, and a dielectric spacer is formed in the cavity.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: February 19, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Haigou Huang