Patents Examined by Marc Armand
  • Patent number: 10109711
    Abstract: Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Stephen M Cea, Roza Kotlyar, Harold W Kennel, Anand S Murthy, Glenn A Glass, Kelin J Kuhn, Tahir Ghani
  • Patent number: 10109289
    Abstract: Systems and methods are disclosed for capturing sound for communication by mounting one or more intra-oral microphones to capture sound; and mounting a mouth wearable communicator in the oral cavity to communicate sound with a remote unit.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: October 23, 2018
    Assignee: SoundMed, LLC
    Inventors: Reza Kassayan, John Spiridigliozzi
  • Patent number: 10109592
    Abstract: A semiconductor device includes a semiconductor chip having a first main surface, a second main surface opposite to the first main surface, and a side wall surface. An electrical contact area is exposed at the side wall surface of the semiconductor chip. An electrically conducting layer covers at least partially the second main surface and the electrical contact area.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: October 23, 2018
    Assignee: Infineon Technologies AG
    Inventor: Chee Yang Ng
  • Patent number: 10109604
    Abstract: A package for embedding one or more electronic components comprises a carrier structure a silicon-based carrier layer, one or more electronic components embedded in one or more cavities formed in the carrier layer, and a cover structure arranged on top of the carrier structure. The cover structure comprises a cover layer and one or more cavities formed in the cover layer. An antenna element and/or a waveguide for connection to an antenna element is formed in and/or on top of the cover layer and coupled to the one or more cavities.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: October 23, 2018
    Assignee: SONY CORPORATION
    Inventors: Ali Eray Topak, Marcel Daniel Blech
  • Patent number: 10109740
    Abstract: An antifuse device includes a gate structure formed on a substrate including first spacers formed in an upper portion and a conductive material formed in a lower portion below the first spacers. Two conductive regions are disposed adjacent to the gate structure and on opposite sides of the gate structure. A dielectric barrier is formed between the conductive material and each of the conductive regions such that a dual antifuse is formed across the dielectric barrier between the conductive material and the conductive regions on each side of the gate structure.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: October 23, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten
  • Patent number: 10109641
    Abstract: According to one embodiment, the electrode films are stacked with gaps interposed between the electrode films. The first insulating film is provided between a lowermost electrode film of the electrode films and the substrate and being a metal oxide film, a silicon carbide film, or a silicon carbonitride film. The second insulating film is provided on an uppermost electrode film of the electrode films and being a metal oxide film, a silicon carbide film, or a silicon carbonitride film. The stacked film includes a semiconductor film extending in a stacking direction of the stacked body in the stacked body, and a charge storage film provided between the semiconductor film and the electrode films.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: October 23, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Shinya Arai
  • Patent number: 10109663
    Abstract: A chip package including a substrate is provided. The substrate has a first surface and a second surface opposite thereto. The substrate includes a sensing region. A cover plate is on the first surface and covers the sensing region. A shielding layer covers a sidewall of the cover plate and extends towards the second surface. The shielding layer has an inner surface adjacent to the cover plate and has an outer surface away from the cover plate. The length of the outer surface extending towards the second surface is less than that of the inner surface extending towards the second surface, and is not less than that of the sidewall of the cover plate. A method of forming the chip package is also provided.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: October 23, 2018
    Assignee: XINTEC INC.
    Inventors: Yu-Lung Huang, Tsang-Yu Liu, Yi-Ming Chang, Hsin Kuan
  • Patent number: 10109491
    Abstract: Vertical channel field effect transistors include a bottom source/drain layer. One or more vertical channels are formed on the bottom source/drain layer. A horizontal seed layer is formed around the one or more vertical channels. A metal gate is formed directly on the seed layer. A top source/drain is formed layer above the one or more vertical channels and the metal gate.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: October 23, 2018
    Assignee: INTENATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10109628
    Abstract: Techniques are disclosed for improving gate control over the channel of a transistor, by increasing the effective electrical gate length (Leff) through deposition of a gate control layer (GCL) at the interfaces of the channel with the source and drain regions. The GCL is a nominally undoped layer (or substantially lower doped layer, relative to the heavily doped S/D fill material) that can be deposited when forming a transistor using replacement S/D deposition. The GCL can be selectively deposited in the S/D cavities after such cavities have been formed and before the heavily doped S/D fill material is deposited. In this manner, the GCL decreases the source and drain underlap (Xud) with the gate stack and further separates the heavily doped source and drain regions. This, in turn, increases the effective electrical gate length (Leff) and improves the control that the gate has over the channel.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: October 23, 2018
    Assignee: INTEL CORPORATION
    Inventors: Anand S. Murthy, Nick Lindert, Glenn A. Glass
  • Patent number: 10103143
    Abstract: An electronic device is provided. The electronic device comprises a fin transistor formed over a substrate which is structured to include a device isolation region and an active region, the fin transistor including: a layer formed over the substrate and having a trench crossing the device isolation region and the active region; a gate filled in the trench; a first fin formed over and overlapping the active region and protruding over the device isolation region; and second fins formed on both sidewalls of the first fin in a direction of the trench.
    Type: Grant
    Filed: September 5, 2016
    Date of Patent: October 16, 2018
    Assignee: SK hynix Inc.
    Inventor: Hubert Alexandre
  • Patent number: 10103330
    Abstract: A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance variable layer has a first portion which is disposed over the sidewall surface of the first electrode and a second portion which extends from the first portion away from the first electrode. A second electrode is over the resistance variable layer.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: October 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chi Tu, Chih-Yang Chang, Hsia-Wei Chen, Yu-Wen Liao, Chin-Chieh Yang, Wen-Ting Chu
  • Patent number: 10103101
    Abstract: A semiconductor device includes: a first interconnection line and a second interconnection line which extend apart from each other on a first plane at a first level on a substrate; a bypass interconnection line that extends on a second plane at a second level on the substrate; and a plurality of contact plugs for connecting the bypass interconnection line to the first interconnection line and the second interconnection line. A method includes forming a bypass interconnection line spaced apart from a substrate and forming on a same plane a plurality of interconnection lines connected to the bypass interconnection line via a plurality of contact plugs.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: October 16, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je-min Park, Dae-ik Kim
  • Patent number: 10103090
    Abstract: The semiconductor device includes a semiconductor element, and an electro-conductive first plate-like part electrically connected to a top-face-side electrode of the semiconductor element and including a first joint part projecting from a side face, and an electro-conductive second plate-like part including a second joint part projecting from a side face. A bottom face of the first joint part and a top face of the second joint part face one another, and are electrically connected via an electro-conductive bonding material. A bonding-material-thickness ensuring means is provided in a zone where the bottom face of the first joint part and the top face of the second joint part face one another to ensure a thickness of the electro-conductive bonding material between an upper portion of a front end of the second joint part and the bottom face of the first joint part.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: October 16, 2018
    Assignees: Toyota Jidosha Kabushiki Kaisha, Denso Corporation
    Inventors: Takuya Kadoguchi, Takahiro Hirano, Takanori Kawashima, Keita Fukutani, Tomomi Okumura, Masayoshi Nishihata
  • Patent number: 10103080
    Abstract: The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a first mold compound component, and a thermally enhanced mold compound component. The first mold compound component resides over the module substrate, surrounds the thinned flip chip die, and extends above an upper surface of the thinned flip chip die to form a cavity over the upper surface of the thinned flip chip die. The thermally enhanced mold compound component includes a lower portion filling a lower region of the cavity and residing over the upper surface of the thinned flip chip die, and an upper portion filling an upper region of the cavity and residing over the lower portion. A first average thermal conductivity of the lower portion is at least 1.2 times greater than a second average thermal conductivity of the upper portion.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: October 16, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim, Dirk Robert Walter Leipold, Baker Scott, Merrill Albert Hatcher, Jr., Stephen Mobley
  • Patent number: 10103224
    Abstract: A semiconductor structure includes a trench isolation structure and a trench capping layer positioned over the trench isolation structure, wherein the trench isolation layer includes a first electrically insulating material and the trench capping layer includes a second electrically insulating material that is different from the first electrically insulating material. The semiconductor structure also includes a gate structure having a gate insulation layer and a gate electrode positioned over the gate insulation layer, wherein the gate insulation layer includes a high-k material and the gate structure includes a first portion that is positioned over the trench capping layer. A sidewall spacer is positioned adjacent to the gate structure, wherein a portion of the sidewall spacer is positioned on the trench capping layer and contacts the trench capping layer laterally of the gate insulation layer.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: October 16, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Elliot John Smith, Steffen Sichler
  • Patent number: 10103246
    Abstract: A method of forming a vertical fin field effect transistor with a self-aligned gate structure, comprising forming a plurality of vertical fins on a substrate, forming gate dielectric layers on opposite sidewalls of each vertical fin, forming a gate fill layer between the vertical fins, forming a fin-cut mask layer on the gate fill layer, forming one or more fin-cut mask trench(es) in the fin-cut mask layer, and removing portions of the gate fill layer and vertical fins not covered by the fin-cut mask layer to form one or more fin trench(es), and two or more vertical fin segments from each of the plurality of vertical fins, having a separation distance, D1, between two vertical fin segments.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: October 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10096490
    Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: October 9, 2018
    Assignee: UTAC HEADQUARTERS PTE. LTD.
    Inventors: Saravuth Sirinorakul, Suebphong Yenrudee
  • Patent number: 10096613
    Abstract: According to one embodiment, columnar portions extend through an insulating layer and through a stacked body under the insulating layer. The columnar portions are of an insulating material different from the insulating layer. Contact portions include a first contact portion disposed inside a first terrace portion and a second contact portion disposed inside a second terrace portion. The columnar portions including a first columnar portion disposed inside the first terrace portion and a second columnar portion disposed inside the second terrace portion. A shortest distance between the first contact portion and the first columnar portion, and a shortest distance between the second contact portion and the second columnar portion are substantially equal to each other.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: October 9, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Atsushi Takahashi, Yasuhito Yoshimizu
  • Patent number: 10090195
    Abstract: A method includes forming a diffusion barrier over a semiconductor structure. The formation of the diffusion barrier includes performing a first tantalum deposition process, the first tantalum deposition process forming a first tantalum layer over the semiconductor structure, performing a treatment of the first tantalum layer, and performing a second tantalum deposition process after the treatment of the first tantalum layer. The treatment modifies at least a portion of the first tantalum layer. The second tantalum deposition process forms a second tantalum layer over the first tantalum layer.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: October 2, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Frank Koschinsky, Bernd Hintze, Heiko Weber
  • Patent number: 10090315
    Abstract: According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: October 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yoshiaki Fukuzumi, Hideaki Aochi