Patents Examined by Marc Duncan
  • Patent number: 10896119
    Abstract: An input-output circuit is coupled to a plurality of serial communication paths and to a physical point-to-point interface. The input-output circuit is configured to transmit data received on the plurality of serial communication paths over the physical point-to-point interface. An application circuit is coupled to the input-output circuit and is configured to communicate via a first one of the paths in performing application functions. A bridge circuit is coupled to the input-output circuit and is configured to communicate via a second one of the paths. A debug circuit is coupled to the application circuit and to the bridge circuit. The debug circuit is configured to capture debug data of the application circuit and provide the debug data to the bridge circuit for communication via the second one of the paths.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: January 19, 2021
    Assignee: Xilinx, Inc.
    Inventors: Ahmad R. Ansari, Felix Burton, Henry C. Yu
  • Patent number: 10892014
    Abstract: In a memory controller included in a memory system for processing a program operation fail, the memory controller controls a plurality of memory devices commonly coupled to a channel, the plurality of memory devices respectively performing preset program operations, and includes: a buffer memory for storing data to be stored in the plurality of memory devices, based on a buffer memory index; and a program error processor for acquiring fail data corresponding to a program operation fail from a fail memory device and acquiring reprogram data that is data to be stored together with the fail data, based on the buffer memory index.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: January 12, 2021
    Assignee: SK hynix Inc.
    Inventors: Hoe Seung Jung, Joo Young Lee
  • Patent number: 10885427
    Abstract: Methods for determining a fixed point format for one or more layers of a DNN based on the portion of the output error of the DNN attributed to the fixed point formats of the different layers. Specifically, in the methods described herein the output error of a DNN attributable to the quantisation of the weights or input data values of each layer is determined using a Taylor approximation and the fixed point number format of one or more layers is adjusted based on the attribution. For example, where the fixed point number formats used by a DNN comprises an exponent and a mantissa bit length, the mantissa bit length of the layer allocated the lowest portion of the output error may be reduced, or the mantissa bit length of the layer allocated the highest portion of the output error may be increased. Such a method may be iteratively repeated to determine an optimum set of fixed point number formats for the layers of a DNN.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: January 5, 2021
    Assignee: Imagination Technologies Limited
    Inventor: James Imber
  • Patent number: 10877853
    Abstract: A data storage device may include: a storage unit comprising a storage comprising a storage area divided into a plurality of blocks, and a controller configured to control a data input/output operation on the storage according to a request of a host device, collect information on a block, of the plurality of blocks, involved in a background operation which is performed while power is supplied, store the collected information as hint information, and resume a background operation started before a sudden power-off, based on the hint information, when power is resupplied after the sudden power-off.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: December 29, 2020
    Assignee: SK hynix Inc.
    Inventors: Se Ho Lee, Min Gu Kang
  • Patent number: 10877844
    Abstract: A plurality of stripe zones are mapped across drives in an array. A capacity of each of the stripe zones is smaller than or equal to an average size of the drives. A failed drive is determined in the array. A deletable stripe zone is selected that is being used for user data storage. The deletable stripe zone is taken offline and used to rebuild a subset of the plurality of the stripe zones affected by the failed drive.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: December 29, 2020
    Assignee: Seagate Technology LLC
    Inventors: Michael Barrell, Ian Davies
  • Patent number: 10866850
    Abstract: A memory device includes a memory module and a control module. The control module is coupled to the memory module and is configured to store data into the memory module according to a first mapping table. The control module includes a storing unit and a guaranteeing unit. The storing unit is configured to store the first mapping table. The guaranteeing unit is coupled to the storing unit and is configured to determine whether the first mapping table is correct or not. The guaranteeing unit is further configured to issue an error signal in a state where the first mapping table is incorrect.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: December 15, 2020
    Assignee: RAYMX MICROELECTRONICS CORP.
    Inventors: Yen-Chung Chen, Cheng-Yu Chen, Chih-Ching Chien
  • Patent number: 10866868
    Abstract: In various embodiments, the system includes augmented database drivers that are configured to automatically retry execution of write operations if a failure is encountered. In some embodiments, a database daemon is configured to manage the database functionality for a respective database node (e.g., primary or secondary node). Retrying execution of write operations allows the drivers to automatically retry certain write operations a threshold number of times if, for example, a network error is encountered, or if a healthy primary node is not available.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: December 15, 2020
    Assignee: MongoDB, Inc.
    Inventor: Eliot Horowitz
  • Patent number: 10866802
    Abstract: Disclosed embodiments relate to identifying Electronic Control Unit (ECU) anomalies in a vehicle. Operations may include monitoring data representing real-time processing activity of the ECU; receiving comparable data relating to processing activity of at least one other ECU deemed comparable in functionality to the ECU; comparing the real-time processing activity data with the comparable data, to identify at least one anomaly in the real-time processing activity of the ECU; and implementing a control action for the ECU when the at least one anomaly is identified.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: December 15, 2020
    Assignee: Aurora Labs Ltd.
    Inventor: Zohar Fox
  • Patent number: 10860407
    Abstract: An apparatus and method for testing and troubleshooting systems, such as remote systems, have been developed that provide for a test control system configured to perform testing on a system under test. The test control system may include an electronic device operable to display a system fault code failure matrix visualization that may include fault codes and/or fault locations for one or more subsystems of a SUT. The test control system may also include an aggregated subsystem fault locations database that stores previously identified system or subsystem fault locations of the SUT that may lead to a source of an issue causing a particular fault code for the SUT, where the electronic device is operable to access the aggregated subsystem fault locations database to obtain the various previously identified fault locations. The previously identified system or subsystem fault locations may be based on previous testing of a system or subsystem.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: December 8, 2020
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventor: Paul Ly
  • Patent number: 10860485
    Abstract: The disclosure relates to embodiments, implemented at least partially in microcode, that use cache misses to trigger logging to a processor trace. One embodiment relies on tracking bits in a processor cache. During a transition from a non-logged context to a logged context, this embodiment invalidates or evicts cache lines whose tracking bits are not set. When logging, this first embodiment logs during cache misses, and sets tracking bits for logged cache lines. Another embodiment relies on way-locking. This second embodiment assigns first ways to a logged entity and second ways to a non-logged entity. The second embodiment ensures the logged entity cannot read cache lines from the second logging ways by flushing the second way during transitions from non-logging to logging, ensures the logged entity cannot read non-logged cache lines from the first ways, and logs based on cache misses into the first ways while executing a logged context.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: December 8, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventor: Jordi Mola
  • Patent number: 10846184
    Abstract: An information handling system may include a first power supply for a first system, a second power supply for a second system, and a management controller. The management controller may detect that the first power supply has failed, receive first information from the first system related to the operation of the first power supply prior to the failure of the first power supply, receive second information from the second system associated with the second power supply, and determine a probability of failure of the second power supply based upon a comparison of the first information with the second information.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: November 24, 2020
    Assignee: Dell Products, L.P.
    Inventors: Sunil Lingappa, Santosh Kumar Sahu, Ajaya K. Senapati, Vaideeswaran Ganesan
  • Patent number: 10824528
    Abstract: Disclosed are hardware and techniques for testing computer processes in a network system by simulating computer process faults and identifying risk associated with correcting the simulated fault and identifying computer processes that may depend on the corrected computer process. The interdependent computer processes in a network may be determined by evaluating a risk matrix having a risk score and non-functional requirement score. An analysis of the risk score and non-functional requirement score accounts for interdependencies between computer processes and identified corrective actions that may be used to determine an optimal network environment. The optimal network environment may be updated dynamically based on changing computer process interdependencies and the determined risk and robustness scores.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: November 3, 2020
    Assignee: Capital One Services, LLC
    Inventors: Bhavik Gudka, Eric Barnum
  • Patent number: 10817358
    Abstract: A system and method for the distributed analysis of high frequency transaction trace data to constantly categorize incoming transaction data, identify relevant transaction categories, create per-category statistical reference and current data and perform statistical tests to identify transaction categories showing overall statistically relevant performance anomalies. The relevant transaction category detection considers both the relative transaction frequency of categories compared to the overall transaction frequency and the temporal stability of a transaction category over an observation duration. The statistical data generated for the anomaly tests contains next to data describing the overall performance of transactions of a category also data describing the transaction execution context, like the number of concurrently executed transactions or transaction load during an observation period.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: October 27, 2020
    Assignee: Dynatrace LLC
    Inventors: Otmar Ertl, Ernst Ambichl
  • Patent number: 10789113
    Abstract: Methods, apparatuses, systems, and devices are described for improving data durability in a data storage system. In one example method of improving data durability, a hardware failure risk indicator may be determined for each of a plurality of data storage elements in the data storage system. The method may also include storing one or more replicas of a first data object on one or more of the plurality of data storage elements, with a quantity of the one or more replicas and a distribution of the one or more replicas among the plurality of data storage elements being a function of the hardware failure risk indicators for each of the plurality of data storage elements. In some examples, the hardware failure risk indicators may be dynamically updated based on monitored conditions, which may result in dynamic adjustments to the quantity and distribution of the data object replicas.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: September 29, 2020
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Dimitar Vlassarev, Andrei Khurshudov
  • Patent number: 10789142
    Abstract: Disclosed are hardware and techniques for testing computer processes in a network system by simulating computer process faults and identifying risk associated with correcting the simulated fault and identifying computer processes that may depend on the corrected computer process. The interdependent computer processes in a network may be determined by evaluating a risk matrix having a risk score and non-functional requirement score. An analysis of the risk score and non-functional requirement score accounts for interdependencies between computer processes and identified corrective actions that may be used to determine an optimal network environment. The optimal network environment may be updated dynamically based on changing computer process interdependencies and the determined risk and robustness scores.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: September 29, 2020
    Assignee: Capital One Services, LLC
    Inventors: Bhavik Gudka, Eric Barnum
  • Patent number: 10776205
    Abstract: Techniques are disclosed for managing data storage. In one embodiment, the techniques determine one or more RAID extents having a disk extent supported by an extent of storage on a storage device in an inoperative state. Each of the RAID extents contains a respective set of disk extents allocated to that RAID extent and each disk extent is supported by an extent of storage on a storage device of the set of storage devices. The techniques also comprise evaluating a set of values, wherein each value indicates, for a corresponding pair of storage devices from the set of storage devices, a number of RAID extents which contain disk extents belonging to both storage devices of the pair.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: September 15, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Wayne Weihua Li, Jian Gao, Jamin Kang, Sheng Wang, Charles Chun Ma
  • Patent number: 10754721
    Abstract: Disclosed herein are systems, devices, and methods related to assets and asset operating conditions. In particular, examples involve defining and using a predictive model that is configured to output an indication of whether at least one failure type from the group of possible failure types is likely to occur at an asset within the given period of time in the future.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: August 25, 2020
    Assignee: UPTAKE TECHNOLOGIES, INC.
    Inventors: Michael Horrell, John Ciasulli, Sheng Zhong, Jason Kolb
  • Patent number: 10747288
    Abstract: A method and system for power management of storage drives. The method includes selecting an initial predetermined dual bit pattern that corresponds to a select power state of the storage drive, for providing to a first and second bit pin of a bit pin pair of a power control circuit that respectively connects to the storage drive. The method includes providing the initial predetermined dual bit pattern to the power control circuit which generates a discrete signal to the storage drive. The method includes encoding the initial predetermined dual bit pattern on the first bit pin and the second bit pin to selectively implement a power change on the storage drive in response to identification of a fault condition. In response to detection of the fault condition, the method includes selectively managing power to the storage drive based on input of the discrete signal.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: August 18, 2020
    Assignee: Dell Products, L.P.
    Inventor: Ryan C. McDaniel
  • Patent number: 10747631
    Abstract: Embodiments described herein provide a mission-critical artificial intelligence (AI) processor (MAIP), which includes an instruction buffer, processing circuitry, a data buffer, command circuitry, and communication circuitry. During operation, the instruction buffer stores a first hardware instruction and a second hardware instruction. The processing circuitry executes the first hardware instruction, which computes an intermediate stage of an AI model. The data buffer stores data generated from executing the first hardware instruction. The command circuitry determines that the second hardware instruction is a hardware-initiated store instruction for transferring the data from the data buffer. Based on the hardware-initiated store instruction, the communication circuitry transfers the data from the data buffer to a memory device of a computing system, which includes the mission-critical processor, via a communication interface.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: August 18, 2020
    Assignee: DINOPLUSAI HOLDINGS LIMITED
    Inventors: Yujie Hu, Tong Wu, Xiaosong Wang, Zongwei Zhu, Chung Kuang Chin, Clifford Gold, Steven Sertillange, Yick Kei Wong
  • Patent number: 10733069
    Abstract: In a data storage system including a non-volatile random access memory (NVRAM) array, a page is a smallest granularity of the NVRAM array that can be accessed by read and write operations, and a memory block containing multiple pages is a smallest granularity of the NVRAM array that can be erased. Data are stored in the NVRAM array in page stripes distributed across multiple memory blocks. In response to detection of an error in a particular page of a particular block of the NVRAM array, only the particular page of the particular block is retired, such that at least two of the multiple memory blocks across which a particular one of the page stripes is distributed include differing numbers of active (non-retired) pages.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Ioannis Koltsidas, Roman A. Pletka, Andrew D. Walls