Abstract: Various embodiments comprise systems and methods to indicate when errors occur in a data pipeline. In some examples, data monitoring circuitry monitors the operations of a data pipeline. The data monitoring circuitry ingests an output data set generated by the pipeline, compares the output data set to an expected output, identifies differences between the output data set and the expected output, and determines when the magnitude of the difference exceeds an error threshold. When the error threshold is exceeded, the data monitoring circuitry generates a graphical representation of the output data set, a graphical representation of the expected pipeline output, and an animated transition from the graphical representation of the expected pipeline output to the graphical representation of the output data.

Abstract: Methods and apparatuses for online replacement of a node enclosure are provided. A storage array system includes a node-pair housed in a node enclosure. Each node of the node-pair are be linked to a network and further linked to each other by external interconnects, independent of the enclosure. The interconnects couple the first storage node to the second storage node externally of the node enclosure. The node-pairs are configured to communicate independently of the node enclosure and the enclosure is replaceable without disruption of communication over the network.

Abstract: Systems, apparatuses, and methods related to data stripe protection are described. An error management component can process multiple read/write/recovery requests concurrently. When read/write requests are to be processed on respective strips of a stripe, the error management component can process (e.g., concurrently) the read/write requests to determine a quantity of errors within each one of the strips and the determined quantity can be used to further determine whether to access other memory portions to correct the determined quantity.

Abstract: Blockchains operate as decentralized, self-regulating systems that involve contributions from hundreds of thousands of participants who work on the verification and authentication of transactions occurring on the blockchain. The consensus mechanism within such a system provides the set of rules that determine the legitimacy of contributions made by the various participants of the blockchain. The consensus mechanism should not only be tolerant of faults but also have low latency in establishing consensus. Prior art solutions either could tolerate at most (n+1)/5 faults reaching consensus or execution of three or more communication steps to provide tolerance of arbitrary (Byzantine) faults or cannot guarantee strong safety property for an honest primary. To improve the speed of the consensus mechanism the inventors have established a BFT consensus protocol that operates with just two communication steps.

Abstract: A vehicle electronic control device, which is mounted on a vehicle and executes a predetermined function of the vehicle, includes: a main processor; a sub processor; and an abnormality determination unit comparing a calculation result of the main processor with a calculation result of the sub processor and determining an abnormality in the main processor based on a comparison result. The predetermined function is performed by a main process executed by the main processor according to a main program. A sub program executed by the sub processor is capable of executing the predetermined function equivalent to the predetermined function of the main program. The sub program provides an improved performance than the main program by having a configuration that differs in part or in whole from a configuration of the main program.

Abstract: A processing device in a host system detecting a failure of a memory sub-system coupled to the host system and collects debug information from the memory sub-system via a memory sub-system interface. Responsive to determining that the debug information is not sufficient to correct the failure of the memory sub-system, the processing device performing an authentication process to authenticate the system to the memory sub-system, collects enhanced debug information from the memory sub-system via the memory sub-system interface, and performs one or more corrective actions based on the enhanced debug information to correct the failure of the memory sub-system.

Abstract: Techniques are disclosed relating to maintaining a high availability (HA) database. In some embodiments, a computer system receives, from a plurality of host computers, a plurality of requests to access data stored in a database implemented using a plurality of clusters. In some embodiments, the computer system responds to the plurality of requests by accessing data stored in an active cluster. The computer system may then determine, based on the responding, health information for ones of the plurality of clusters, wherein the health information is generated based on real-time traffic for the database. In some embodiments, the computer system determines, based on the health information, whether to switch from accessing the active cluster to accessing a backup cluster. In some embodiments, the computer system stores, in respective clusters of the database, a changeover decision generated based on the determining.

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

Abstract: Examples described herein relate to execution of multiple Reliability Availability Serviceability (RAS) processes on different processors of the at least two processors to provide fallback from a first RAS process to a second RAS process executing on a processor of the at least two processors based on failure or timeout of the first RAS process. In some examples, the different processors comprise independently operating processors whereby failure or inoperability of one of the different processors is independent of another of the different processors. In some examples, failure or timeout of the first RAS process comprises failure of the second RAS process to receive an operating status signal from the first RAS process.

Abstract: A patching operation on an availability group cluster having a plurality of nodes is disclosed. The patching operation is performed in a plurality of iterations, each including determining a current state of each of the plurality of nodes, selecting a next node based on the current state, and patching the next node. A secondary replica node is selected as the next node before the a primary replica node. Each secondary replica node is patched in accordance with a first priority, upon patching each of the secondary replica node, a failover target node for patching the primary replica node is selected, the failover target node is selected based on a second priority, and according to the second priority, a healthy synchronous secondary replica node of the plurality of nodes is selected as the failover target node before an unhealthy synchronous secondary replica node of the plurality of nodes.

Abstract: Methods, systems, and devices for programming failure handling during data folding are described. A memory system may support a non-blocking exception handling process for handling program failures that occur during folding. For example, if a program failure occurs at a given page, the memory system may mark the failed page as storing uncorrectable data (e.g., associated with an uncorrectable error correction code (UECC) error) rather than as being associated with the program failure. Based on the marking, the memory system may continue the folding operation, allowing the data to be moved to another page of a physical destination block. After the folding operation is complete, the memory system may replace a failed physical destination block that includes the failed page with a spare block and retire the failed physical destination block.

Abstract: A data protection method and system are provided. At least one computing device provides information representing failure of a drive that is assigned to a RAID group. Available storage on each of a plurality of drives in use in the RAID group is identified and at least one virtual drive is built using at least the available storage. Data associated with the failed drive is provided to the virtual drive(s). The virtual drive(s) is/are assigned to the RAID group, and appears to be the failed drive in a non-failed state. Information representing the failed drive having been replaced is received and data from the at least one virtual drive is provided to the replacement drive. The replacement drive is assigned to the RAID group. The replacement drive appears to the RAID controller to be the failed drive. The virtual drive(s) are released.

Abstract: In a storage system including a plurality of storage nodes and a plurality of storage devices that provide storage areas to the storage nodes, a cluster control unit that has detected occurrence of a failure in another storage node requests an external control device to execute a detach process of detaching a storage device allocated to a failure storage node from the failure storage node and an attach process of allocating the storage device to an alternative storage node. Then, the alternative cluster control unit restores, based on a log stored in a storage device allocated to a storage node in which a most recent failure has occurred among the storage nodes belonging to the same redundancy group as a failure storage control unit of the failure storage node, storage content of a memory of the alternative storage node.

Abstract: A system board backup and restore system includes a computing device, a storage device that is housed in the computing device and that includes a CMB device, and a replacement system board that is housed in the computing device, that is coupled to the storage device, and that includes a replacement system board BMC device. During initialization of the computing device, the replacement system board BMC device identifies the CMB device. Subsequent to identifying the CMB device, the replacement system board BMC device retrieves first firmware from the CMB device that was backed up in the CMB device by a replaced system board BMC device included on a replaced system board that was previously housed in the computing device and coupled to the storage device. The replacement system board BMC device then installs the first firmware on replacement system board subsystem(s) included on the replacement system board.

Abstract: A method may include: receiving a plurality of log-text examples from network devices and labels indicating if the log-text example is anomalous or not anomalous; identifying, from the log-text examples and labels, rules for weak annotation, and validation labels for a validation dataset and test labels for a test dataset; organizing log-text examples in the validation dataset into a plurality of time windows; concatenating log-text examples in each time window; providing the concatenated log-text examples and the rules for weak annotation to a weak annotation framework, to a LLM training dataset; training a LLM with the LLM training dataset; collecting runtime log-texts from the network devices for a period of time; concatenating the runtime log-texts for the period of time; and prompting the LLM for analysis with the concatenated log-texts, wherein the LLM outputs a response of anomaly or no anomaly and a confidence in the response.

Abstract: An information handling system that includes a processor and a memory coupled to the processor, the memory having program instructions stored thereon that upon execution cause the processor to determine a last audit date of a machine learning model, such as a language model in response to detecting a connection to an edge device. The execution of the program instructions may also cause the processor to determine whether the last audit date exceeds an audit threshold and apply an error correction code to the language model in response to a determination that the last audit date exceeds the audit threshold.

Abstract: A system includes: a processor; a register configured to store a plurality of words, non-volatile memory having a plurality of cells, each cell corresponding to one of the words of the register, and wherein the each cell of the plurality of cells are set to an initial reset value; a first controller that in response to a loss in power: determines the word stored by the register; and changes the initial reset value of the cell of the non-volatile memory corresponding to the determined word stored by the register to a set value; a second controller that in response to detecting a restoration in power: identifies the cell having the set value; writes the word corresponding to the identified cell to the register; and resets the cells of the non-volatile memory to the initial reset value.

Abstract: Methods, systems, and products for sustainable Reliability, Availability, and Serviceability (RAS) balancing based on predictive models includes predicting, based on one or more predictive models, a potential failure within a computing system, and provisioning, based on the potential failure, one or more redundant resources for failover.

Abstract: An embodiment of an electronic apparatus may include one or more substrates, and logic coupled to the one or more substrates, the logic to control access to a persistent storage media based on a block and sub-block access structure, store a data structure in the persistent storage media to track read fails at a sub-block granularity for a word-line for every block, and update the data structure in response to a read fail on a block to indicate a failed sub-block that corresponds to the read fail for a word-line for the block. Other embodiments are disclosed and claimed.

Abstract: In an embodiment of the disclosed technology, a data storage device includes at least one memory device including a plurality of memory regions configured to store data, a first controller configured to allocate the plurality of memory regions according to a memory allocation request of one or more host devices, and a second controller configured to: generate, in response to a snapshot request of a first host device among the one or more host devices, snapshot data corresponding to at least part of the data stored in at least part of the plurality of memory regions allocated to the first host device; and store the snapshot data into an auxiliary storage device coupled to the second controller.