Abstract: A semiconductor device includes a substrate, an isolation structure on the substrate, a fin protruding from the substrate and through the isolation structure, a gate stack engaging the fin, and a gate spacer on sidewalls of the gate stack. The gate spacer includes an inner sidewall facing the gate stack and an outer sidewall opposing the inner sidewall. The inner sidewall has a first height measured from a top surface of the fin and a bowed structure in a top portion of the inner sidewall. The bowed structure extends towards the gate stack for a first lateral distance measured from a middle point of the inner sidewall. The first lateral distance is less than about 8% of the first height.

Abstract: A semiconductor device includes first to third electrodes, a semiconductor part, a control electrode and an insulating body. The second electrode is opposite to the first electrode. The semiconductor part is provided between the first electrode and the second electrode. The semiconductor part includes first and second trenches next to each other in a front side facing the second electrode. The second trench has a first width in a first direction directed from the first trench toward the second trench. The third electrode and the control electrode are provided inside the first trench. Another third electrode and the insulating body is provided inside the second trench. The insulating body is positioned in the second trench between said another third electrode and the second electrode. The insulating body has a second width in the first direction. The second width is equal to the first width of the second trench.

Abstract: According to one embodiment, a semiconductor storage device includes a stacked body, a columnar body, a conductive member, a plate-like portion, and a dividing portion. In the stacked body, a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one, and a stepped portion including the conductive layers is formed to be faced to an end in a first direction. The columnar body penetrates the stacked body, and includes a memory cell formed in a portion facing the conductive layer. The conductive member is electrically connected to the columnar body below the stacked body, and extends to a region laterally below the stacked body beyond the stepped portion in the first direction. The plate-like portion extends in a stacking direction of the stacked body in a lateral region of the stacked body to reach the conductive member, and extends in a second direction intersecting the first direction.

Abstract: A display apparatus includes a substrate including a first pixel area and a second pixel area adjacent to each other, a first insulating layer disposed on the substrate, where a first groove or a first opening corresponding to a boundary between the first pixel area and the second pixel area and a second groove or a second opening corresponding to the boundary between the first pixel area and the second pixel area are defined in the first insulating layer, and the second groove or the second opening is spaced apart from the first groove or the first opening, and a first conductive layer disposed over the first insulating layer, where the first conductive layer includes a first conductive pattern disposed in the first pixel area, a second conductive pattern disposed in the second pixel area, and a bridge connecting the first conductive pattern to the second conductive pattern.

Abstract: An integrated circuit device includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a first insulating layer on the first surface of the semiconductor substrate, an electrode landing pad positioned on the first surface of the semiconductor substrate and having a sidewall surrounded by the first insulating layer, a top surface apart from the first surface of the semiconductor substrate, and a bottom surface opposite to the top surface, and a through-electrode configured to penetrate through the semiconductor substrate and contact the top surface of the electrode landing pad, wherein a horizontal width of the top surface of the electrode landing pad is less than a horizontal width of the bottom surface of the electrode landing pad and greater than a horizontal width of a bottom surface of the through-electrode in contact with the top surface of the electrode landing pad.

Abstract: The present disclosure relates to a pixel comprising: a photodiode comprising a portion of a substrate of a semiconductor material, extending vertically from a first face of the substrate to a second face of the substrate configured to receive light; a layer of a first material covering each of the lateral surfaces of the portion; a layer of a second material covering the portion on the side of the first face, first and second material having refractive indexes lower than that of the semiconductor material; and a diffractive structure disposed on a face of the photodiode on the side of the second face.

Abstract: An electroplating cup assembly comprises a cup bottom, a lip seal, and an electrical contact structure. The cup bottom at least partially defines an opening configured to allow exposure of a wafer positioned in the cup assembly to an electroplating solution. The lip seal is on the cup bottom and comprises a sealing structure extending upwardly along an inner edge of the lip seal to a peak that is configured to be in contact with a seed layer of a wafer and adjacent to a sacrificial layer of the wafer. The electrical contact structure is over a portion of the seal. The electrical contact structure configured to be coupled to the seed layer of the wafer.

Abstract: A display substrate, a method of manufacturing a display substrate, and an electronic device are provided. The display substrate includes: a base substrate; a thin film transistor arranged on the base substrate; a first planarization layer arranged on a side of the thin film transistor away from the base substrate; a first protective layer arranged on a side of the first planarization layer away from the base substrate; a first conductive layer arranged on a side of the first protective layer away from the base substrate; and a second planarization layer arranged on a side of the first conductive layer away from the base substrate, wherein the display substrate is provided with a first via hole penetrating the first protective layer, and the first planarization layer is in contact with the second planarization layer through the first via hole.

Abstract: According to one embodiment, a semiconductor memory device includes a stacked layer body including conductive and insulating layers alternately stacked in a first direction, partition structures each extending in first and second directions in the stacked layer body, and an intermediate structure extending from an upper end and terminating at a position between upper and lower ends of the stacked layer body between adjacent partition structures. The partition structures include a first partition structure including first and second portions arranged in the second direction, the first portion extends from the upper end to the lower end, and the second portion is located between adjacent first portions, extends from the upper end and terminates at the position between the upper and lower ends.

Abstract: A package comprising a substrate, a first antenna device, and an integrated device. The substrate comprising a first surface and a second surface, where the substrate comprises a plurality of interconnects. The first antenna device is coupled to the first surface of the substrate, through a first plurality of solder interconnects. The integrated device is coupled to the second surface of the substrate. The package may include an encapsulation layer located over the second surface of the substrate, where the encapsulation layer encapsulates the integrated device. The package may include a shield formed over a surface of the encapsulation layer, where the shield includes an electromagnetic interference (EMI) shield.

Abstract: The present application provides a reworking method of a failed hard mask layer on a via opening in a dielectric layer, including removing the failed hard mask layer; forming an underfill layer to fill the via opening; forming a top hard mask layer on the underfill layer; and forming a mask layer on the top hard mask layer.

Abstract: A described example includes: a semiconductor die having bond pads on a device side surface; a passivation layer overlying the device side surface of the semiconductor die with openings in the passivation layer, the passivation layer having a planar surface facing away from the device side surface of the semiconductor die; post connects formed on the bond pads and in the openings in the passivation layer, the post connects having a proximate end on the bond pads and extending from the bond pads to a distal end that lies beneath the planar surface of the passivation layer; solder at the distal ends of the post connects and contacting sidewalls of the openings in the passivation layer; and solder joints formed between the solder at the distal ends of the post connects and a package substrate, the device side surface of the semiconductor die facing the package substrate.

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

Abstract: A semiconductor device having favorable electrical characteristics is provided.

Abstract: The present disclosure provides a display panel and a display device. The display panel includes: a base substrate, a display region including a first region, a second region and a transition region; first light-emitting elements at the first region; second light-emitting elements, first pixel circuitries and second pixel circuitries at the transition region, each first pixel circuitry being arranged between adjacent second pixel circuitries, an orthogonal projection of at least one second pixel circuitry onto the base substrate at least partially overlapping an orthogonal projection of at least one second light-emitting element onto the base substrate; first conductive lines each coupled between at least one first pixel circuitry and at least one first light-emitting element; and second conductive lines each coupled to at least one first pixel circuitry and extending along the at least one first pixel circuitry to a side away from the at least one first light-emitting element.

Abstract: In an embodiment an apparatus includes a delimiting device and a holding device configured to hold the delimiting device at a distance above an optoelectronic light-emitting device and form a layer of a material provided in a flowable state between the delimiting device and the light-emitting device, wherein a bottom side of the delimiting device, which faces the light-emitting device, has a structuring so that a structure complementary to the structuring is producible on an upper side of the layer.

Abstract: A display panel and a display device are provided. The display panel includes a bending region and a non-bending region, and the bending region is distributed on a periphery of the non-bending region. The display panel further includes a first functional layer and a second functional layer disposed on a first encapsulation layer. The second functional layer is disposed in the bending region. A refractive index of the second functional layer is greater than a refractive index of the first functional layer. An embodiment of the present invention improves display effects of the display panel.

Abstract: A process for obtaining a nitride (N) layer preferably obtained from at least one of gallium (Ga), indium (In) and aluminium (Al), may include: on a stack including a substrate and at least the following layers successively disposed from the substrate: a creep layer having a glass transition temperature, Tglass transition, and a crystalline layer, forming pads by etching the stack so that each pad includes at least a creep segment formed by at least a portion of the creep layer, and a crystalline segment formed by the crystalline layer; and growing by epitaxy a crystallite on each of the pads and continuing the epitaxial growth of the crystallites so as to form the nitride layer. The epitaxial growth may be carried out at a temperature Tepitaxy, such that Tepitaxy?k1×Tglass transition, with k1 being 0.8.

Abstract: The present disclosure concerns a method for fabricating a magnetoresistive element comprising a magnetic tunnel junction including a tunnel barrier layer, a first ferromagnetic layer and a second ferromagnetic layer; a writing current layer; and an interconnect layer configured for supplying the writing current to the writing current layer. A gap is provided in the interconnect layer such that the latter comprises two discontinuous interconnect segments extending along a layer plane and connecting the writing current layer in series. The method comprises: depositing the interconnect layer, writing current layer, second ferromagnetic layer, tunnel barrier layer and first ferromagnetic layer; forming the gap in the interconnect layer; filling the gap with the gap material; and forming the pillar by performing a single etch step until the interconnect layer, acting as a stop layer, is reached.

Abstract: A unit pixel of a Red-Green-Cyan-Blue (RGCB) microdisplay is disclosed. In the unit pixel, sub-pixels that form blue light, green light, cyan light, and red light, are vertically stacked on a growth substrate. Accordingly, the unit pixel area may be reduced, and pixel transfer processing is facilitated.