Patents Examined by Marcos D. Pizarro
  • Patent number: 11031547
    Abstract: A ferromagnetic layer is capped with a metallic oxide (or nitride) layer that provides a perpendicular-to-plane magnetic anisotropy to the layer. The surface of the ferromagnetic layer is treated with a plasma to prevent diffusion of oxygen (or nitrogen) into the layer interior. An exemplary metallic oxide layer is formed as a layer of metallic Mg that is plasma treated to reduce its grain size and enhance the diffusivity of oxygen into its interior. Then the plasma treated Mg layer is naturally oxidized and, optionally, is again plasma treated to reduce its thickness and remove the oxygen rich upper surface.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Guenole Jan, Ru-Ying Tong
  • Patent number: 11031358
    Abstract: A method for forming a sensor with increased overhang to prevent passivation stress fractures is provided. Embodiments include forming a first passivation layer over a dielectric layer patterned over a first top metal layer of a logic region of a sensor and a second top metal layer of an array region of the sensor; planarizing the first passivation layer and the dielectric layer to form a level surface above the first top metal layer and the second top metal layer; etching the dielectric layer to form a pad opening in the array region of the sensor based on a predetermined overhang value, the pad opening exposing a portion of the surface of the second top metal layer; and forming a second passivation layer over the level surface and the pad opening in the array region.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 8, 2021
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Aarthi Sridharan, Gong Cheng, Premachandran Chirayarikathuveedu, Fahad Mirza, Carole Graas, Sricharan Tubati, Nurul Islam Mohd
  • Patent number: 11031537
    Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: June 8, 2021
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Richard G. Harris, Andrew J. Berkley, Jan Johansson, Mark Johnson, Mohammad Amin, Paul I. Bunyk
  • Patent number: 11031286
    Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Yip Loh, Chih-Wei Chang, Hong-Mao Lee, Chun-Hsien Huang, Yu-Ming Huang, Yan-Ming Tsai, Yu-Shiuan Wang, Hung-Hsu Chen, Yu-Kai Chen, Yu-Wen Cheng
  • Patent number: 11031371
    Abstract: The present technology relates to a semiconductor package. The semiconductor package comprises: a first component comprising a plurality of first dies stacked on top of each other, each of first dies comprising at least one side surface and an electrical contact exposed on the side surface, and the plurality of first dies aligned so that the corresponding side surfaces of all first dies substantially coplanar with respect to each other to form a common sidewall; a first conductive pattern formed over the sidewall and at least partially spaced away from the sidewall, the first conductive pattern electrically interconnecting the electrical contacts of the plurality of first dies; at least one second component; and a second conductive pattern formed on a surface of the second component, the second conductive pattern affixed and electrically connected to the first conductive pattern formed over the sidewall of the first component.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: June 8, 2021
    Assignee: SanDisk Information Technology (Shanghai) Co., Ltd.
    Inventors: Chin Tien Chiu, Tiger Tai, Ken Qian, C C Liao, Hem Takiar, Gursharan Singh
  • Patent number: 11018218
    Abstract: The present disclosure, in some embodiments, relates to a method of semiconductor processing. The method may be performed by etching a substrate to define a trench within the substrate. A sacrificial material is formed within the trench. The sacrificial material has an exposed upper surface. A plurality of discontinuous openings are formed to expose separate segments of a sidewall of the sacrificial material. The plurality of discontinuous openings are separated by non-zero distances along a length of the trench. An etching process is performed to simultaneously etch the exposed upper surface and the sidewall of the sacrificial material.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuei-Sung Chang, Te-Hao Lee
  • Patent number: 11011689
    Abstract: A quantum dot LED package is disclosed. The quantum dot LED package includes: a heat dissipating reflector having a through cavity; a quantum dot plate accommodated in the upper portion of the through cavity; an LED chip accommodated in the lower portion of the through cavity and whose top surface is coupled to the lower surface of the quantum dot plate; electrode pads disposed on the lower surface of the LED chip and protruding more downward than the lower surface of the heat dissipating reflector; and a resin part formed in the through cavity to fix between the LED chip and the reflector and between the quantum dot plate and the reflector.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: May 18, 2021
    Assignee: LUMENS CO., LTD.
    Inventors: Sunghwan Yoo, Dohyoung Kang, Sungsik Jo
  • Patent number: 11011483
    Abstract: A packaged semiconductor die includes a semiconductor die coupled to a die pad. The semiconductor die has a front side containing copper leads, a copper seed layer coupled to the copper leads, and a nickel alloy coating coupled to the copper seed layer. The nickel alloy includes tungsten and cerium (NiWCe). The packaged semiconductor die may also include wire bonds coupled between leads of a lead frame and the copper leads of the semiconductor die. In addition, the packaged semiconductor die may be encapsulated in molding compound. A method for fabricating a packaged semiconductor die. The method includes forming a copper seed layer over the copper leads of the semiconductor die. In addition, the method includes coating the copper seed layer with a nickel alloy. The method also includes singulating the semiconductor wafer to create individual semiconductor die and placing the semiconductor die onto a die pad of a lead frame.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: May 18, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Nazila Dadvand, Christopher Daniel Manack, Salvatore Frank Pavone
  • Patent number: 11011601
    Abstract: The present disclosure, in some embodiments, relates to a semiconductor structure. The semiconductor structure includes a substrate. As viewed from a top-view, the substrate has a first sidewall, one or more second sidewalls, and a plurality of third sidewalls. The first sidewall extends along a first direction and defines a first side of a trench. The one or more second sidewalls extends along the first direction and define a second side of the trench. The plurality of third sidewalls are oriented in parallel and extends in a second direction perpendicular to the first direction. The plurality of third sidewalls protrude outward from the second side of the trench and define a plurality of parallel releasing openings that are separated along the first direction by the substrate. The trench continuously extends in opposing directions past the plurality of parallel releasing openings.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuei-Sung Chang, Te-Hao Lee
  • Patent number: 11004854
    Abstract: A semiconductor device includes an active region in a substrate, an isolation film defining the active region in the substrate, a gate trench extending across the active region and the isolation film and including a first trench in the active region and a second trench in the isolation film, a gate electrode including a main gate electrode and a pass gate electrode, the main gate electrode filling a lower part of the first trench, and the pass gate electrode filling a lower part of the second trench, a support structure on the pass gate electrode, the support structure filling an upper part of the second trench, a gate insulating film interposed between the isolation film and the pass gate electrode and between the support structure and the pass gate electrode.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: May 11, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ki-Hyung Nam
  • Patent number: 11004936
    Abstract: Insulated gate semiconductor device includes drift layer of first conductivity type; first base region of second conductivity type on the drift layer; carrier-supply region of the first conductivity type on the first base region and having higher impurity concentration than the drift layer; a first contact region of the second conductivity type on the first base region and having higher impurity concentration than the first base regions; cell-pillars each having polygonal-shape, arranged in a lattice-pattern, sidewalls of the cell-pillars are defined by trenches penetrating the carrier-supply region, the first contact region, and the first base region; and insulated-gate electrode-structures in the trenches. A first pillar selected from the cell-pillars includes the carrier-supply region, the first contact region and the first base region, and the first contact regions are in contact with a limited portion of an outer periphery of a first pillar at a top surface of the first pillar.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 11, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Syunki Narita
  • Patent number: 11004991
    Abstract: Provided is a method of manufacturing a photovoltaic solar cell, including: forming a first conductivity type region that contains a first conductivity dopant, on one surface of a semiconductor substrate and an opposite surface that is opposite to the one surface; removing the first conductivity type region formed on the opposite surface of the semiconductor substrate by performing dry etching; and forming a second conductivity type region that contains a second conductivity type dopant, on the opposite surface of the semiconductor substrate.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: May 11, 2021
    Assignee: LG ELECTRONICS INC.
    Inventors: Younggu Do, Sungjin Kim, Hyungwook Choi
  • Patent number: 10998492
    Abstract: Provided is a Hall element which is reduced in asymmetrically generated offset voltage. A semiconductor device includes: a semiconductor layer of a first conductivity type having a Hall element forming region; an element isolation region of the first conductivity type having a concentration higher than a concentration of the semiconductor layer, the element isolation region being formed so as to surround the Hall element forming region; and a Hall element formed in the Hall element forming region and comprising a magnetism sensing portion of a second conductivity type which is higher in concentration than the semiconductor layer and which is kept apart from the element isolation region through the semiconductor layer.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: May 4, 2021
    Assignee: ABLIC INC.
    Inventor: Tatsuya Aso
  • Patent number: 10998345
    Abstract: The present disclosure provides a display panel. The display panel includes: data lines located in the display area, arranged in a first direction, extending in a second direction, and including first and second data lines, and a cross-voltage range of the first data line being smaller than that of the second data line; and fanout traces located in the fanout area and including first and second fanout traces located between first and second edges, and the first fanout trace being connected to the first data line and the second fanout trace being connected to the second data line. A length of the first edge is longer than a length of the second edge, the first edge and the second edge are oppositely arranged in the second direction, and a line width d1 of the first fanout trace is smaller than a line width d2 of the second fanout trace.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: May 4, 2021
    Assignee: Shanghai Tianma AM-OLED Co., Ltd.
    Inventors: Mengmeng Zhang, Xingyao Zhou, Yue Li, Shuai Yang
  • Patent number: 10998264
    Abstract: A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: May 4, 2021
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Jun Hu, Madhur Bobde, Hamza Yilmaz
  • Patent number: 10991669
    Abstract: A semiconductor package is provided. The semiconductor package includes a semiconductor device bonded to a base through a first conductive structure. The semiconductor device includes a carrier substrate including a conductive trace. A portion of the conductive trace is elongated. The semiconductor device also includes a second conductive structure above the carrier substrate. A portion of the second conductive structure is in contact with the portion of the conductive trace. The semiconductor device further includes a semiconductor body mounted above the conductive trace. The semiconductor body is connected to the second conductive structure.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: April 27, 2021
    Assignee: MediaTek Inc.
    Inventors: Che-Ya Chou, Wen-Sung Hsu, Nan-Cheng Chen
  • Patent number: 10985145
    Abstract: A light source module including a substrate and a plurality of light emitting units is provided. The light emitting units are disposed on a surface of the substrate and each light emitting unit includes a first light emitting device, a second light emitting device, a first reflective element, a second reflective element and a package structure. The first reflective element and the second reflective element are respectively overlapped with the first light emitting device and the second light emitting device along a direction being perpendicular to the surface of the substrate. The package structure is disposed between the first reflective element, the second reflective element, the first light emitting device and the second light emitting device. The package structure includes a main body portion and a first recess. The main body portion covers the first light emitting device and the second light emitting device.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: April 20, 2021
    Assignee: Coretronic Corporation
    Inventors: Shih-Yi Lin, Wen-Hsun Yang, Yu-An Huang
  • Patent number: 10985105
    Abstract: A method of forming a contact to a semiconductor device is provided that forms an alloy composed of nickel (Ni), platinum (Pt), aluminum (Al), titanium (Ti) and a semiconductor material. The methods may include forming a nickel and platinum semiconductor alloy at a base of a via. A titanium layer having an angstrom scale thickness is deposited in the via in contact with the nickel platinum semiconductor alloy. An aluminum containing fill is deposited atop the titanium layer. A forming gas anneal including an oxygen containing atmosphere is applied to the structure to provide a contact alloy comprising nickel, platinum, aluminum, titanium and a semiconductor element from the contact surface of the semiconductor device.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: April 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Bruley, Jack O. Chu, Kam-Leung Lee, Ahmet S. Ozcan, Paul M. Solomon, Jeng-bang Yau
  • Patent number: 10978641
    Abstract: A vapor deposition mask capable of correctly performing confirmation of whether a shape pattern of openings formed in a resin mask is normal or similar confirmation while satisfying both high definition and lightweight, a vapor deposition mask preparation body for obtaining the vapor deposition mask, a frame-equipped vapor deposition mask including the vapor deposition mask, and a method for producing an organic semiconductor element using the frame-equipped vapor deposition mask. The aforementioned problem is solved by using, in a vapor deposition mask including a metal mask in which a through hole is formed and a resin mask in which an opening corresponding to a pattern to be produced by vapor deposition is formed at a position overlapping with the through hole, the metal mask and the resin mask being stacked, wherein the resin mask has about 40% or less of light ray transmittance at a wavelength of about 550 nm.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: April 13, 2021
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Toshihiko Takeda, Hiroshi Kawasaki, Katsunari Obata
  • Patent number: 10978548
    Abstract: A method of forming an integrated capacitor on a semiconductor surface on a substrate includes etching a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate which is above and electrically isolated from the semiconductor surface to provide at least one defined dielectric feature having sloped dielectric sidewall portion. A dielectric layer is deposited to at least partially fill pits in the sloped dielectric sidewall portion to smooth a surface of the sloped dielectric sidewall portion. The dielectric layer is etched, and a top plate is then formed on top of the dielectric feature.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: April 13, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Elizabeth Costner Stewart, Jeffrey A. West, Thomas D. Bonifield, Joseph Andre Gallegos, Jay Sung Chun, Zhiyi Yu