Patents Examined by Marcos D. Pizarro
  • Patent number: 10658554
    Abstract: An LED lamp is formed from a die substrate wherein the substrate has formed thereon a semiconductor material, an electrode for the application of a bias across the semiconductor material for causing light to be emitted therefrom, and an adhesive that bonds the die substrate to a support substrate, wherein the adhesive is a polymerized siloxane polymer having a thermal conductivity of greater than 0.1 watts per meter kelvin (W/(m·K)) wherein the adhesive is not light absorbing, wherein the siloxane polymer has silicon and oxygen in the polymer backbone, as well as aryl or alky groups bound thereto, and wherein the adhesive further comprises particles having an average particle size of less than 100 microns.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: May 19, 2020
    Assignee: Inkron Oy
    Inventors: Juha Rantala, Jarkko Heikkinen, Janne Kylmä
  • Patent number: 10658232
    Abstract: An interconnect layout structure, having a plurality of air gaps, includes a substrate having an insulating material disposed thereon and a conductive line disposed in the insulating material and extending along a first direction. The air gaps are formed in the insulating material and are arranged end-to-end along the first direction and immediately adjacent to a same side of the conductive line. A patterned hard mask is disposed on the conductive line and has a sidewall extending along a second direction that is perpendicular to the first direction and passing between the adjacent air gaps from the top view. A via structure is formed on the conductive line and is electrically connected to the conductive line.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: May 19, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tong-Yu Chen, Chia-Fang Lin
  • Patent number: 10651154
    Abstract: A semiconductor package includes a plurality of semiconductor chips on a substrate. The semiconductor chips include a first semiconductor chip, a second semiconductor chip, and a third semiconductor chip that are sequentially stacked on the substrate. The semiconductor package further includes a plurality of non-conductive layers between the substrate and the first semiconductor chip and between adjacent semiconductor chips among the semiconductor chips. The semiconductor chips include smaller widths as a distance from the substrate increases. Each of the non-conductive layers includes an extension protruding outward from a side surface of an overlying one of the semiconductor chips.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: May 12, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Sick Park, Geol Nam, Tae Hong Min, Jihwan Hwang
  • Patent number: 10644016
    Abstract: A structure and method for providing improved and reliable charge trapping memory device are disclosed herein. A charge trapping field effect transistor (FET) comprising a semiconductor substrate, a doped region in the semiconductor substrate, and a gate structure on the semiconductor substrate and a method of fabricating the same are also discussed. The doped region comprises a first lateral dimension along a first direction. The gate structure comprises a charge trapping dielectric region and a charge trapping conductive region in contact with the charge trapping dielectric region.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: May 5, 2020
    Assignee: Cypress Semiconductor Corporation
    Inventors: Kuo Tung Chang, Shenqing Fang, Timothy Thurgate
  • Patent number: 10644229
    Abstract: A method of fabricating a semiconductor device includes forming a stack of film comprising an anti-ferromagnetic layer, the pin layer, a barrier layer, a free layer and a bottom electrode layer. The method also includes forming a first patterned hard mask over the anti-ferromagnetic layer, etching the anti-ferromagnetic layer and the pin layer by using the first patterned hard mask as a first etch mask, forming a first capping layer along sidewalls of the anti-ferromagnetic layer and the pin layer, etching the barrier layer and the free layer by using first patterned hard mask and the first capping layer as a second etch mask, forming a second capping layer over the first capping layer and extending along sidewalls of the barrier layer and the free layer, exposing the anti-ferromagnetic layer and forming a top electrode layer over the exposed anti-ferromagnetic layer.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: May 5, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chern-Yow Hsu
  • Patent number: 10636703
    Abstract: A semiconductor device which prevents a crack from occurring on a pad region is provided. The semiconductor device includes a lower pad, an upper pad which is formed above the lower pad, an insulation layer which is formed between the lower pad and the upper pad, a via net for electrically connecting the lower pad and the upper pad in the insulation layer, the via net having a net shape in which a unit grid is connected with its adjacent unit grids to form a net structure, and at least one via hole for electrically connecting the lower pad and the upper pad in the unit grid of the via net.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: April 28, 2020
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Jong-yeul Jeong
  • Patent number: 10636730
    Abstract: A semiconductor package includes a semiconductor substrate structure, a semiconductor die and an encapsulant. The semiconductor substrate structure includes a dielectric structure, a first patterned conductive layer, a first insulation layer and a conductive post. The first patterned conductive layer is embedded in the dielectric structure. The first insulation layer is disposed on the dielectric structure. The conductive post connects to the first patterned conductive layer and protrudes from the first insulation layer. The first insulation layer has a greater thickness at a position closer to the conductive post. The semiconductor die is electrically connected to the conductive post. The encapsulant covers the semiconductor die and at least a portion of the semiconductor substrate structure.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: April 28, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Cheng-Lin Ho, Chih-Cheng Lee, Li-Chuan Tsai
  • Patent number: 10636803
    Abstract: A semiconductor memory device includes a semiconductor member extending in a first direction, a first interconnect extending in a second direction crossing the first direction, and a first electrode disposed between the semiconductor member and the first interconnect. A curvature radius of a corner portion facing the semiconductor member in the first electrode is larger than a curvature radius of a corner portion facing the first interconnect in the first electrode.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: April 28, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Tatsuya Kato, Fumitaka Arai, Kohei Sakaike, Satoshi Nagashima
  • Patent number: 10629516
    Abstract: Structures for field-effect transistors and methods for fabricating a structure for field-effect transistors. A contact structure is formed that includes a first contact arranged over a source/drain region and a second contact arranged over the first contact. A dielectric cap is formed over the second contact. A via is formed that extends in a vertical direction through the dielectric cap to the second contact. An interconnect is formed over the dielectric cap, and is connected by the via with the second contact.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: April 21, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel Chanemougame, Julien Frougier, Ruilong Xie
  • Patent number: 10629497
    Abstract: A semiconductor device structure and a method for forming the same are provided. The semiconductor device structure includes a first fin structure protruding from the first region of the semiconductor substrate and having a first portion and a second portion over the first portion. The semiconductor device structure also includes a liner structure including a first insulating liner layer and second insulating liner layer. The first insulating liner layer has a bottom portion covering the semiconductor substrate and a sidewall portion covering a sidewall of the first portion of the first fin structure. The second insulating liner layer is over the bottom portion and the sidewall portion of the first insulating liner layer and extends on a top surface of the sidewall portion of the first insulating liner layer. The semiconductor device structure also includes an isolation feature over the liner structure.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: April 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Han-Pin Chung, Jian-Shiou Huang
  • Patent number: 10618801
    Abstract: Microelectromechanical systems (MEMS) packages and methods for forming the same are provided. The MEMS package includes a semiconductor substrate having a metallization layer over the semiconductor substrate. The MEMS package also includes a first planarization layer and an overlying second planarization layer over the metallization layer. The planarization structure has a first cavity therein exposing the metallization layer. The MEMS package also includes a MEMS device structure bonded to the second planarization layer. The MEMS device structure includes a moveable element over the first cavity. The MEMS package also includes a first stopper placed on the exposed metallization layer in the first cavity. The first stopper includes a patterned conductive layer and an underlying patterned insulating layer.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: April 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Chuan Tai, Hsiang-Fu Chen, Fan Hu
  • Patent number: 10615078
    Abstract: After forming a material stack including a gate dielectric, a work function metal and a cobalt gate electrode in a gate cavity formed by removing a sacrificial gate structure, the cobalt gate electrode is recessed by oxidizing the cobalt gate electrode to provide a cobalt oxide layer on a surface of the cobalt gate electrodes and removing the cobalt oxide layer from the surface of the cobalt gate electrodes by a chemical wet etch. The oxidation and oxide removal steps can be repeated until the cobalt gate electrode is recessed to any desired thickness. The work function metal can be recessed after the recessing of the cobalt gate electrode is completed or during the recessing of the cobalt gate electrode.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: April 7, 2020
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES INC., LAM RESEARCH CORPORATION
    Inventors: Georges Jacobi, Vimal K. Kamineni, Randolph F. Knarr, Balasubramanian Pranatharthiharan, Muthumanickam Sankarapandian
  • Patent number: 10615236
    Abstract: Disclosed is a display device that with low power consumption. The display device includes a first thin film transistor having a polycrystalline semiconductor layer in an active area and a second thin film transistor having an oxide semiconductor layer in the active area, wherein at least one opening disposed in a bending area has the same depth as one of a plurality of contact holes disposed in the active area, whereby the opening and the contact holes are formed through the same process, and the process is therefore simplified, and wherein a high-potential supply line and a low-potential supply line are disposed so as to be spaced apart from each other in the horizontal direction, whereas a reference line and the low-potential supply line are disposed so as to overlap each other, thereby preventing signal lines from being shorted.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: April 7, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Kyoung-Nam Lim, Yu-Ho Jung, Dong-Young Kim
  • Patent number: 10615333
    Abstract: The vertical Hall element includes: a semiconductor layer of a second conductivity type formed on a semiconductor substrate of a first conductivity type; a first electrode set formed in a surface of the semiconductor layer and including a first drive current supply electrode, a Hall voltage output electrode, and a second drive current supply electrode aligned along a straight line extending in a first direction in this order; and second to fifth electrode sets each having the same configuration as the configuration of the first electrode set and aligned with the first electrode set along a straight line extending in a second direction perpendicular to the first direction. The Hall voltage output electrode has a first depth, the first and second drive current supply electrodes have a second depth that is larger than the first depth.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: April 7, 2020
    Assignee: ABLIC INC.
    Inventor: Takaaki Hioka
  • Patent number: 10607955
    Abstract: A device may include a fan-out structure that has a plurality of integrated circuits. The integrated circuits may be of different types, such as by being configured differently or configured to perform different functions. The fan-out structure may be coupled to another integrated circuit structure, such as a die stack. For example, the fan-out structure may be coupled to a top surface or a bottom surface of the integrated circuit structure, or may otherwise be disposed within a vertical profile defined by the integrated circuit structure. Horizontally-extending and vertically-extending paths may be disposed in between and around the combined fan-out structure and integrated circuit structure to enable the integrated circuits of the two structures to communicate.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: March 31, 2020
    Assignee: SanDisk Semiconductor (Shanghai) Co. Ltd.
    Inventors: Chin-Tien Chiu, Chih-Chin Liao, Weiting Jiang, Hem Takiar
  • Patent number: 10608093
    Abstract: A semiconductor device and a method of forming the same are disclosed. First, a substrate having a main surface is provided. At least a trench is formed in the substrate. A barrier layer is formed in the trench and a conductive material is formed on the barrier layer and filling up the trench. The barrier layer and the conductive material are then recessed to be lower than the upper surface of the substrate. After that, an oxidation process is performed to oxidize the barrier layer and the conductive material thereby forming an insulating layer.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: March 31, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chia-Wei Wu, Ting-Pang Chung, Tien-Chen Chan, Shu-Yen Chan
  • Patent number: 10600899
    Abstract: Provided is a low cost semiconductor device in which occurrence of chipping and a crack during dicing is suppressed. A nitride layer (silicon nitride layer) 23 is formed on an oxide layer 22. In FIG. 1, a thick organic layer 24 is formed as a top layer. The semiconductor device 1 is characterized by its structure on a side of its end portion. In FIG. 1, the end portion E of the semiconductor device 1 is formed by cutting with a blade in the vertical direction during dicing. An edge E1 of both the oxide layer 22 and the nitride layer is located apart from an edge of a semiconductor substrate 10. An edge E2 of the organic layer 24 on the nitride layer 23 is located inside the edge E1 of the nitride layer 23 (on a side more distant from the edge E).
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: March 24, 2020
    Assignee: Sanken Electric Co., Ltd.
    Inventor: Hironori Aoki
  • Patent number: 10600902
    Abstract: A self repairing field effect transistor (FET) device, in accordance with one embodiment, includes a plurality of FET cells each having a fuse link. The fuse links are adapted to blow during a high current event in a corresponding cell.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: March 24, 2020
    Assignee: Vishay Siliconix, LLC
    Inventor: Robert Xu
  • Patent number: 10593766
    Abstract: Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate materials, and laterally removing a portion of each of the tier control gate materials to form control gate recesses. A charge blocking material comprising a charge trapping portion is formed on exposed surfaces of the tier dielectric materials and tier control gate materials in the opening. The control gate recesses are filled with a charge storage material. The method further comprises removing the charge trapping portion of the charge blocking material disposed horizontally between the charge storage material and an adjacent tier dielectric material to produce air gaps between the charge storage material and the adjacent tier dielectric material. The air gaps may be substantially filled with dielectric material or conductive material. Also disclosed are semiconductor structures obtained from such methods.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: March 17, 2020
    Assignee: Micron Technology, Inc.
    Inventor: John D. Hopkins
  • Patent number: 10593774
    Abstract: An electronic device can include a transistor having a drain region, a source region, a dielectric layer, and a gate electrode. The dielectric layer can have a first portion and a second portion, wherein the first portion is relatively thicker and closer to the drain region; the second portion is relatively thinner and closer to the source region. The gate electrode of the transistor can overlie the first and second portions of the dielectric layer. In another aspect, an electronic device can be formed using two different dielectric layers having different thicknesses. A gate electrode within the electronic device can be formed over portions of the two different dielectric layers. The process can eliminate masking and doping steps that may be otherwise used to keep the drain dopant concentration closer to the concentration as originally formed.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: March 17, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Gary H. Loechelt, Gordon M. Grivna