Patents Examined by Marcos D. Pizarro
-
Patent number: 12206056Abstract: Provided is a method of fabricating a semiconductor package. The method of fabricating the semiconductor package include preparing a lower element including a lower substrate, a lower electrode, an UBM layer, and a reducing agent layer, providing an upper element including an upper substrate, an upper electrode, and a solder bump layer, providing a pressing member on the upper substrate to press the upper substrate to the lower substrate, and providing a laser beam passing through the pressing member to bond the upper element to the lower element.Type: GrantFiled: August 11, 2021Date of Patent: January 21, 2025Assignee: Electronics and Telecommunications Research InstituteInventors: Kwang-Seong Choi, Yong Sung Eom, Jiho Joo, Gwang-Mun Choi, Seok-Hwan Moon, Chanmi Lee, Ki Seok Jang
-
Patent number: 12199023Abstract: An electronic apparatus includes an integrated circuit board on, over, or in which a USB circuit block is provided; a first USB interface; a second USB interface; a printed circuit board on which a source clock circuit configured to output a source clock is provided; and a ball grid array that includes first, second, and third ball grids for electric coupling between the integrated circuit board and the printed circuit board. The first ball grid electrically couples the USB circuit block and the first USB interface to each other. The second ball grid electrically couples the USB circuit block and the second USB interface to each other. The third ball grid electrically couples the source clock circuit and the USB circuit block to each other. The third ball grid is located between the first ball grid and the second ball grid.Type: GrantFiled: September 2, 2021Date of Patent: January 14, 2025Assignee: Seiko Epson CorporationInventor: Katsuo Takeuchi
-
Patent number: 12193255Abstract: A display panel, a method of manufacturing the display panel and a display device are provided in the present disclosure. The display panel includes: a substrate, a functional film layer arranged on the substrate, a first bending region capable of being bent along a first direction, a second bending region capable of being bent along a second direction, and a third bending region located between the first bending region and the second bending region. The first direction intersects the second direction. The functional film layer includes a non-hollowed region located in at least one of the first bending region and the second bending region, and a part of the functional film layer located in the third bending region includes a plurality of functional via holes spaced from each other.Type: GrantFiled: April 30, 2020Date of Patent: January 7, 2025Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Tingliang Liu, Xiangdan Dong, Junxi Wang, Yi Zhang, Ming Hu, Mengqi Wang, Siyu Wang, Shun Zhang, Lulu Yang, Jie Dai, Huijuan Yang
-
Patent number: 12192722Abstract: A sound producing cell includes a membrane and an actuating layer. The membrane includes a first membrane subpart and a second membrane subpart, wherein the first membrane subpart and the second membrane subpart are opposite to each other. The actuating layer is disposed on the first membrane subpart and the second membrane subpart. The first membrane subpart includes a first anchored edge which is fully or partially anchored, and edges of the first membrane subpart other than the first anchored edge are non-anchored. The second membrane subpart includes a second anchored edge which is fully or partially anchored, and edges of the second membrane subpart other than the second anchored edge are non-anchored.Type: GrantFiled: September 22, 2023Date of Patent: January 7, 2025Assignee: xMEMS Labs, Inc.Inventors: Chiung C. Lo, Hao-Hsin Chang, Wen-Chien Chen, Chun-I Chang
-
Patent number: 12191151Abstract: A method includes forming a gate stack, growing a source/drain region on a side of the gate stack through epitaxy, depositing a contact etch stop layer (CESL) over the source/drain region, depositing an inter-layer dielectric over the CESL, etching the inter-layer dielectric and the CESL to form a contact opening, and etching the source/drain region so that the contact opening extends into the source/drain region. The method further includes depositing a metal layer extending into the contact opening. Horizontal portions, vertical portions, and corner portions of the metal layer have a substantially uniform thickness. An annealing process is performed to react the metal layer with the source/drain region to form a source/drain silicide region. The contact opening is filled to form a source/drain contact plug.Type: GrantFiled: June 1, 2021Date of Patent: January 7, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jui-Ping Lin, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
-
Patent number: 12183755Abstract: An imaging device and an electronic apparatus that make it possible to reduce color mixture between pixels are provided. An imaging device of an embodiment of the present disclosure includes: a plurality of pixels (PX) each having a stacked structure in which a photoelectric conversion section (PD) including a light entrance surface, a first light transmissive film provided to face the light entrance surface and having a first refractive index (nCF), and a second light transmissive film having a second refractive index (n18) higher than the first refractive index are stacked in order in a stacking direction, the plurality of pixels being arranged in an in-plane direction orthogonal to the stacking direction; and a first pixel separation section provided between a plurality of the first light transmissive films adjacent to each other in the in-plane direction, and having a third refractive index (n13) lower than the first refractive index.Type: GrantFiled: January 17, 2020Date of Patent: December 31, 2024Assignee: Sony Semiconductor Solutions CorporationInventors: Kaito Yokochi, Takayuki Ogasahara
-
Patent number: 12183738Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a cross-coupled gate circuit in a three-dimensional (3D) stack including a plurality of transistors, a first gate line of a first transistor among the plurality of transistors connected to a fourth gate line of a fourth transistor among the plurality of transistors, a second gate line of a second transistor among the plurality of transistors connected to a third gate line of a third transistor among the plurality of transistors, a first conductor connecting the first gate line and the fourth gate line, a second conductor connecting the second gate line and the third gate line. The first gate line and the second gate line are arranged above the third gate line and the fourth gate line, respectively.Type: GrantFiled: April 2, 2021Date of Patent: December 31, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seunghyun Song, Seungyoung Lee, Saehan Park
-
Patent number: 12183830Abstract: A display device includes a metal layer composed of multiple layers including a lowermost layer lower in an ionization tendency than a middle layer, the lowermost layer being in contact with and on the oxide semiconductor layer. Each channel region is interposed between a corresponding one of the first electrodes and a corresponding one of the second electrodes, constituting a corresponding one of the thin film transistors. The oxide semiconductor layer is continuous between a pair of channel regions included in an adjacent pair of thin film transistors. The metal layer is continuous between a pair of first electrodes included in the adjacent pair of thin film transistors.Type: GrantFiled: January 26, 2022Date of Patent: December 31, 2024Assignee: Japan Display Inc.Inventor: Yohei Yamaguchi
-
Patent number: 12170321Abstract: A semiconductor device a method of forming the same are provided. The method includes forming a fin extending from a substrate and forming a gate dielectric layer along a top surface and sidewalls of the fin. A first thickness of the gate dielectric layer along the top surface of the fin is greater than a second thickness of the gate dielectric layer along the sidewalls of the fin.Type: GrantFiled: September 11, 2020Date of Patent: December 17, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuei-Lun Lin, Yen-Fu Chen, Po-Ting Lin, Chia-Yuan Chang, Xiong-Fei Yu, Chi On Chui
-
Patent number: 12166112Abstract: A semiconductor device includes a graphene film disposed on a substrate and formed of atomic layers of graphene that are stacked, a source electrode and a drain electrode disposed on the graphene film, and a gate electrode disposed on the graphene film between the source electrode and the drain electrode with a gate insulator film interposed between the gate electrode and the graphene film, wherein a first number of the atomic layers of the graphene film in a source region where the source electrode is located and a drain region where the drain electrode is located is greater than a second number of the atomic layers of the graphene film in a channel region where the gate electrode is located.Type: GrantFiled: August 10, 2021Date of Patent: December 10, 2024Assignee: Sumitomo Electric Industries, Ltd.Inventors: Yasunori Tateno, Fuminori Mitsuhashi
-
Patent number: 12119238Abstract: A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.Type: GrantFiled: September 30, 2019Date of Patent: October 15, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Meng-Tse Chen, Hsiu-Jen Lin, Wei-Hung Lin, Kuei-Wei Huang, Ming-Da Cheng, Chung-Shi Liu
-
Patent number: 12108630Abstract: Embodiments of the present disclosure are related to a display device, as arranging a storage capacitor and an active pattern disposed on a subpixel by using an active layer that a semiconductor layer and a conductive layer are laminated, an area of the storage capacitor can be increased efficiently and methods can be provided to use an area overlapped with a contact-hole located on the active pattern as an area of the storage capacitor. Furthermore, as a location of the contact-hole is adjusted easily, by making the contact-hole not to be disposed on an area adjacent to a driving transistor, a size of the driving transistor can be increased and an aperture ratio of the subpixel can be improved.Type: GrantFiled: November 30, 2021Date of Patent: October 1, 2024Assignee: LG DISPLAY CO., LTD.Inventors: HyunHaeng Lee, Kiwoong Song
-
Patent number: 12100680Abstract: A semiconductor structure includes: a first base having a first face, a second base having a second face and a welded structure. The first base is provided with an electrical connection column protruding from the first face. A conductive column is provided in the second base, and a first groove and a second groove are further provided at the second face. The first groove is located above the conductive column, and the second groove exposes at least part of a side surface of the conductive column. The protruding portion of the electrical connection column is located in the second groove, and part of a side surface of the electrical connection column and part of the side surface of the conductive column overlap in staggered way in a direction perpendicular to the first face or the second surface. At least part of the welded structure is filled in the first groove.Type: GrantFiled: June 22, 2022Date of Patent: September 24, 2024Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventors: Luguang Wang, Jinrong Huang
-
Patent number: 12094908Abstract: A wide dynamic range with single exposure is achieved. A solid-state imaging device according to an embodiment includes a first substrate including a photoelectric conversion element, and a second substrate including a capacitor positioned on a side opposite to a surface of incidence of light to the photoelectric conversion element in the first substrate, and configured to accumulate a charge transferred from the photoelectric conversion element.Type: GrantFiled: August 6, 2019Date of Patent: September 17, 2024Assignee: Sony Semiconductor Solutions CorporationInventors: Masaaki Takizawa, Yorito Sakano
-
Patent number: 12094897Abstract: An imaging element according to an embodiment of the present disclosure includes: a semiconductor substrate having an effective pixel region in which a plurality of pixels is disposed and a peripheral region provided around the effective pixel region; a photoelectric converter; a first hydrogen block layer; an interlayer insulating layer; and a separation groove. The photoelectric converter includes a first electrode, a second electrode, and an electric charge accumulation layer and a photoelectric conversion layer. The first electrode is provided on a light receiving surface side of the semiconductor substrate and includes a plurality of electrodes. The second electrode is disposed to be opposed to the first electrode. The electric charge accumulation layer and the photoelectric conversion layer are stacked and provided in order between the first electrode and the second electrode and extend in the effective pixel region.Type: GrantFiled: January 27, 2020Date of Patent: September 17, 2024Assignee: Sony Semiconductor Solutions CorporationInventor: Takahiro Kamei
-
Patent number: 12074156Abstract: A memory array includes a first memory cell configured to store data, a second memory cell configured to store data and a bit line extending along the first direction, and being over the first memory cell and the second memory cell. The first memory cell and the second memory cell are arranged along a first direction in a first column of memory cells. The bit line includes a first conductor extending in the first direction and being in a first conductive layer, and a second conductor extending in the first direction and being in a second conductive layer different from the first conductive layer.Type: GrantFiled: March 25, 2021Date of Patent: August 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hidehiro Fujiwara, Sahil Preet Singh, Chih-Yu Lin, Hsien-Yu Pan, Yen-Huei Chen, Hung-Jen Liao
-
Patent number: 12074126Abstract: A semiconductor structure and a method of manufacturing the semiconductor structure are provided. The semiconductor structure includes a substrate including a plurality of pads spaced apart from each other, a first groove, and a second groove connected with the first groove, the first and the second grooves located in the substrate. The first groove is located on the side of the second groove away from the plurality of pads, and the bottom of the second groove exposes a corresponding pad of the plurality of pads. The orthographic projection of the second groove on the substrate is located within the orthographic projection of the first groove on the substrate. A redistribution layer is disposed on a surface of the corresponding pad, the inner wall of the first groove, and the inner wall and the bottom of the second groove. The semiconductor structure prevents contamination or damage of test probes.Type: GrantFiled: April 20, 2022Date of Patent: August 27, 2024Assignee: Changxin Memory Technologies, Inc.Inventors: Liang Wang, Qian Xu
-
Patent number: 12073790Abstract: A display substrate and a display device are provided. The display substrate includes sub-pixels, first data lines, and first power signal lines. The sub-pixel includes a light emitting element including a second electrode. The sub-pixel includes a first connecting portion including a first sub-connecting portion and a first block. The second electrode is overlapped with the first data line, the first power signal line and the first connecting portion, the first power signal line and the first data line are located at both sides of the first connecting portion. A ratio of a minimum distance between edges of the first sub-connecting portion and the first data line which are close to each other to a minimum distance between edges of the first block and the first power signal line which are close to each other is in a range from 0.8 to 1.2.Type: GrantFiled: July 31, 2020Date of Patent: August 27, 2024Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Tinghua Shang, Haigang Qing, Pengfei Yu, Yu Wang, Tingliang Liu, Ling Shi, Yao Huang
-
Patent number: 12074204Abstract: A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate. The fin structure includes a protection layer and alternating first and second semiconductor layers over the protection layer. The method also includes etching the fin structure to form a source/drain recess, forming a sacrificial contact in the source/drain recess, forming a source/drain feature over the sacrificial contact in the source/drain recess, removing the first semiconductor layers of the fin structure, thereby forming a plurality of nanostructures, forming a gate stack wrapping around the nanostructures, removing the substrate thereby exposing the protection layer and the sacrificial contact and replacing the sacrificial contact with a contact plug.Type: GrantFiled: July 23, 2021Date of Patent: August 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jung-Hung Chang, Lo Heng Chang, Zhi-Chang Lin, Shih-Cheng Chen, Chien-Ning Yao, Kuo-Cheng Chiang, Chih-Hao Wang
-
Patent number: 12074132Abstract: A semiconductor device includes a first circuit, a second circuit, a wiring member, and a bonding material. The wiring member is connected to one of the first circuit and the second circuit. The bonding material is connected to the other of the first circuit and the second circuit. The wiring member includes a first end, a second end, and a top. The first end and the second end are connected to one of the first circuit and the second circuit. The top is located between the first end and the second end. The top is connected to the other of the first circuit and the second circuit with the bonding material in between.Type: GrantFiled: May 22, 2019Date of Patent: August 27, 2024Assignee: MITSUBISHI ELECTRIC CORPORATIONInventor: Yo Tanaka