Patents Examined by Marcos D. Pizarro
  • Patent number: 11521956
    Abstract: A method of manufacturing a light-emitting device includes: providing a first intermediate structure including a substrate, light-emitting elements arrayed in a first direction, a protective element, and light-transmissive members; forming a resin wall including first and second walls extending in the first direction, and third and fourth walls, a first distance between the first wall and the light-emitting elements being larger than a second distance between the third or fourth wall and a corresponding one of light-emitting elements; applying a first resin to a first region between the first wall and the light-emitting elements in which the protective element is disposed, resulting in forming a first recess in the first region and a second recess in a second region between the second wall and the light-emitting elements; and forming a covering member by applying a second resin to the first and second recesses and curing the first and second resins.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: December 6, 2022
    Assignee: NICHIA CORPORATION
    Inventors: Shogo Abe, Yuki Ogura
  • Patent number: 11515197
    Abstract: A semiconductor device includes: a substrate; an ion-implanted silicon layer disposed in the substrate; a first insulator layer disposed over the ion-implanted silicon layer; an active device disposed over the first insulator layer; and a conductive via configured to penetrate the first insulator layer for coupling the ion-implanted silicon layer and the active device.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Wei Peng, Wei-Cheng Lin, Jiann-Tyng Tzeng
  • Patent number: 11515457
    Abstract: The present application discloses a light-emitting device comprising a light-emitting unit and a flexible carrier supporting the light-emitting unit. The light-emitting unit comprises a LED chip, a first reflective layer on the LED chip and an optical diffusion layer formed between the first reflective layer and the LED chip.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: November 29, 2022
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Jai-Tai Kuo, Wei-Kang Cheng
  • Patent number: 11508688
    Abstract: The present invention has: a heater; and a bonding tool having a lower surface on which a memory chip is adsorbed; and an upper surface attached to the heater, and is provided with a bonding tool which presses the peripheral edge of the memory chip to a solder ball in a first peripheral area of the lower surface and which presses the center of the memory chip (60) to a DAF having a heat resistance temperature lower than that of the solder ball in a first center area. The amount of heat transmitted from the first center area to the center of the memory chip is smaller than that transmitted from the first peripheral area (A) to the peripheral edge of the memory chip. Thus, the bonding apparatus in which the center of a bonding member can be heated to a temperature lower than that at the peripheral edge can be provided.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: November 22, 2022
    Assignee: SHINKAWA LTD.
    Inventors: Kohei Seyama, Yuji Eguchi, Shoji Wada
  • Patent number: 11508879
    Abstract: A small-sized semiconductor device with a structure for stopping and keeping uncured resin or adhesive in a desired region, which is manufactured by employing a process of curing uncured resin or adhesive that is made to wet and spread on a board, is provided. The semiconductor device includes a board mounted with a semiconductor element and includes metal patterns formed on the board. The metal patterns include a first metal pattern, a second metal pattern, and a through electrode. The first metal pattern and the second metal pattern are provided separately from each other on the board. The through electrode is disposed between the first metal pattern and the second metal pattern and penetrates through the board in the thickness direction.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: November 22, 2022
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventor: Masaki Odawara
  • Patent number: 11502245
    Abstract: A method of fabricating a semiconductor device includes forming a stack of film comprising an anti-ferromagnetic layer, the pin layer, a barrier layer, a free layer and a bottom electrode layer. The method also includes forming a first patterned hard mask over the anti-ferromagnetic layer, etching the anti-ferromagnetic layer and the pin layer by using the first patterned hard mask as a first etch mask, forming a first capping layer along sidewalls of the anti-ferromagnetic layer and the pin layer, etching the barrier layer and the free layer by using first patterned hard mask and the first capping layer as a second etch mask, forming a second capping layer over the first capping layer and extending along sidewalls of the barrier layer and the free layer, exposing the anti-ferromagnetic layer and forming a top electrode layer over the exposed anti-ferromagnetic layer.
    Type: Grant
    Filed: May 4, 2020
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Chern-Yow Hsu
  • Patent number: 11502149
    Abstract: Disclosed is a display device that with low power consumption. The display device includes a first thin film transistor having a polycrystalline semiconductor layer in an active area and a second thin film transistor having an oxide semiconductor layer in the active area, wherein at least one opening disposed in a bending area has the same depth as one of a plurality of contact holes disposed in the active area, whereby the opening and the contact holes are formed through the same process, and the process is therefore simplified, and wherein a high-potential supply line and a low-potential supply line are disposed so as to be spaced apart from each other in the horizontal direction, whereas a reference line and the low-potential supply line are disposed so as to overlap each other, thereby preventing signal lines from being shorted.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: November 15, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: Kyoung-Nam Lim, Yu-Ho Jung, Dong-Young Kim
  • Patent number: 11502134
    Abstract: This disclosure relates to reduced power consumption OLED displays at reduced cost for reduced information content applications, such as wearable displays. Image quality for wearable displays can be different than for high information content smart phone displays and TVs, where the wearable display has an architecture that in includes, for example, an all phosphorescent device and/or material system that may be fabricated at reduced cost. The reduced power consumption can facilitate wireless and solar charging.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: November 15, 2022
    Assignee: Universal Display Corporation
    Inventors: Michael Hack, Julia J. Brown, Michael Stuart Weaver, Woo-Young So
  • Patent number: 11502180
    Abstract: A semiconductor device includes a substrate having at least a trench formed therein. A conductive material fills a lower portion of the trench. A barrier layer is between the conductive material and the substrate. An insulating layer is in the trench and completely covers the conductive material and the barrier layer, wherein a portion of the insulating layer covering the barrier layer has a bird's peak profile.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: November 15, 2022
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chia-Wei Wu, Ting-Pang Chung, Tien-Chen Chan, Shu-Yen Chan
  • Patent number: 11495632
    Abstract: A semiconductor image sensor includes a substrate having a first side and a second side that is opposite the first side. An interconnect structure is disposed over the first side of the substrate. A plurality of radiation-sensing regions is located in the substrate. The radiation-sensing regions are configured to sense radiation that enters the substrate from the second side. A plurality of isolation structures are each disposed between two respective radiation-sensing regions. The isolation structures protrude out of the second side of the substrate.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Lee, Yun-Wei Cheng, Yung-Lung Hsu, Hsin-Chi Chen
  • Patent number: 11495715
    Abstract: An electronic device includes: a support body including first and second planar portions facing each other, a first connecting portion connecting the first and second planar portions, and a first receptacle surrounded by the first and second planar portions and the first connecting portion; a projection being part of the second planar portion projecting outward from the first receptacle outside the first planar portion in plan view; a wiring substrate including a facing surface facing the support body and an opposite surface opposite to the facing surface, the wiring substrate being folded and attached along an inner surface of the first receptacle and a surface of the projection continuous with the inner surface of the first receptacle; a sensor element mounted on the facing surface attached to the inner surface of the first receptacle; and an antenna mounted on the opposite surface attached to the surface of the projection.
    Type: Grant
    Filed: November 10, 2020
    Date of Patent: November 8, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Tatsuaki Denda
  • Patent number: 11469306
    Abstract: A semiconductor device including a substrate having isolation films and active regions that are defined by the isolation films. The active regions extend in a first direction. A first trench is disposed on the substrate. Second trenches are disposed in the active regions. A filling film is disposed in the first trench. First gate patterns are disposed on the filling film in the first trench. Second gate patterns are disposed in the second trenches. The second gate patterns extend in a second direction that is different from the first direction. The filling film includes at least one material selected from a semiconductor material film and a metal.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: October 11, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jee-Sun Lee, Dong Soo Woo, Nam Ho Jeon
  • Patent number: 11469201
    Abstract: The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a conductive trace embedded in a base. A semiconductor device is mounted on the conductive trace via a conductive structure.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: October 11, 2022
    Assignee: MediaTek Inc.
    Inventors: Tzu-Hung Lin, Wen-Sung Hsu, Ta-Jen Yu, Andrew C. Chang
  • Patent number: 11468221
    Abstract: A cell architecture and a method for placing a plurality of cells to form the cell architecture are provided. The cell architecture includes at least a 1st cell and a 2nd cell placed next to each other in a cell width direction, wherein the 1st cell includes a one-fin connector which is formed around a fin among a plurality of fins of the 1st cell, and connects a vertical field-effect transistor (VFET) of the 1st cell to a power rail of the 1st cell, wherein a 2nd cell includes a connector connected to a power rail of the 2nd cell, wherein the fin of the 1st cell and the connector of the 2nd cell are placed next to each other in the cell width direction in the cell architecture, and wherein the one-fin connector of the 1st cell and the connector of the 2nd cell are merged.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: October 11, 2022
    Assignee: SAMSUNG ELECTRONICS CO.. LTD.
    Inventors: Jung Ho Do, Seung Hyun Song
  • Patent number: 11462449
    Abstract: A semiconductor device includes a semiconductor chip provided inside with a p-n junction, an opaque sealing resin covering a surface of the semiconductor chip, and a functional region arranged between the semiconductor chip and the sealing resin and configured to prevent light, which is generated when a forward current flows through the p-n junction and has a particular wavelength causing deterioration of the sealing resin, from reaching the sealing resin.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: October 4, 2022
    Assignee: NISSAN MOTOR CO., LTD.
    Inventors: Hiroshi Sato, Yoshinori Murakami, Hidekazu Tanisawa, Shinji Sato, Fumiki Kato, Kazuhiro Mitamura, Yui Takahashi
  • Patent number: 11462544
    Abstract: An array of recessed access gate lines includes active area regions having dielectric trench isolation material there-between. The trench isolation material comprises dielectric projections extending into opposing ends of individual active area regions under an elevationally outermost surface of material of the active area regions. The active area material is elevationally over the dielectric projections. Recessed access gate lines individually extend transversally across the active area regions and extend between the ends of immediately end-to-end adjacent active area regions within the dielectric trench isolation material. Other arrays are disclosed, as are methods.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: October 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Kamal M. Karda, Wolfgang Mueller, Sourabh Dhir, Robert Kerr, Sangmin Hwang, Haitao Liu
  • Patent number: 11462667
    Abstract: An electronic component includes a wiring substrate having a first surface, a second surface opposite to the first surface, a side surface connected to the first surface and the second surface, and a groove portion formed in the side surface and extending from the first surface to the second surface. The electronic component further includes a first electrode disposed on the first surface along the first surface, a second electrode disposed on the second surface along the second surface, a connection conductor disposed over an entire inner surface of the groove portion and electrically connected to the first electrode and the second electrode, an electronic element disposed on the first surface and electrically connected to the first electrode, and a resin portion disposed on the first surface. All edges of the second electrode are spaced apart from the side surface.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: October 4, 2022
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventors: Fumitaka Nishio, Masatsugu Takatsuka
  • Patent number: 11462470
    Abstract: A method for manufacturing a semiconductor structure includes: forming a dielectric layer over a conductive layer on a semiconductor substrate; etching the dielectric layer to form a via hole that exposes the conductive layer; depositing a barrier layer to line the via hole; after depositing the barrier layer, depositing a first metal layer to fill a remainder of the via hole; performing a chemical mechanical polishing (CMP) process on the first metal layer until the barrier layer is exposed; after performing the CMP process, depositing a second metal layer over the barrier layer and the first metal layer; and etching the second metal layer to form a metal line.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: October 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue
  • Patent number: 11456288
    Abstract: An image display element includes micro light emitting elements arranged in an array, a drive circuit substrate that includes a drive circuit for supplying a current to the micro light emitting elements to cause light to be emitted, and an antenna arranged on a light emitting surface of each of the micro light emitting elements, in which the antenna includes isolated convex portions.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: September 27, 2022
    Assignee: Sharp Fukuyama Laser Co., Ltd.
    Inventors: Hiroaki Onuma, Katsuji Iguchi, Koji Takahashi, Hidenori Kawanishi
  • Patent number: 11456402
    Abstract: A light-emitting device includes: a package defining a recess; a light-emitting element mounted on surface that defines a bottom of the recess; and a sealing member disposed in the recess so as to cover the light-emitting element and made of a light-transmissive resin that contains a filler with an average particle diameter of 200 nm or more and 500 nm or less. The sealing member comprises a filler-containing layer, which contains the filler, and a light-transmissive layer that are layered in an order from a bottom side of the recess. The filler-containing layer has a thickness of equal to or larger than a height of the light-emitting element.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: September 27, 2022
    Assignee: NICHIA CORPORATION
    Inventors: Shogo Abe, Keita Shimizu, Takashi Kadota