Patents Examined by Marcos D. Pizarro
  • Patent number: 11462470
    Abstract: A method for manufacturing a semiconductor structure includes: forming a dielectric layer over a conductive layer on a semiconductor substrate; etching the dielectric layer to form a via hole that exposes the conductive layer; depositing a barrier layer to line the via hole; after depositing the barrier layer, depositing a first metal layer to fill a remainder of the via hole; performing a chemical mechanical polishing (CMP) process on the first metal layer until the barrier layer is exposed; after performing the CMP process, depositing a second metal layer over the barrier layer and the first metal layer; and etching the second metal layer to form a metal line.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: October 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shin-Yi Yang, Ming-Han Lee, Shau-Lin Shue
  • Patent number: 11456402
    Abstract: A light-emitting device includes: a package defining a recess; a light-emitting element mounted on surface that defines a bottom of the recess; and a sealing member disposed in the recess so as to cover the light-emitting element and made of a light-transmissive resin that contains a filler with an average particle diameter of 200 nm or more and 500 nm or less. The sealing member comprises a filler-containing layer, which contains the filler, and a light-transmissive layer that are layered in an order from a bottom side of the recess. The filler-containing layer has a thickness of equal to or larger than a height of the light-emitting element.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: September 27, 2022
    Assignee: NICHIA CORPORATION
    Inventors: Shogo Abe, Keita Shimizu, Takashi Kadota
  • Patent number: 11456288
    Abstract: An image display element includes micro light emitting elements arranged in an array, a drive circuit substrate that includes a drive circuit for supplying a current to the micro light emitting elements to cause light to be emitted, and an antenna arranged on a light emitting surface of each of the micro light emitting elements, in which the antenna includes isolated convex portions.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: September 27, 2022
    Assignee: Sharp Fukuyama Laser Co., Ltd.
    Inventors: Hiroaki Onuma, Katsuji Iguchi, Koji Takahashi, Hidenori Kawanishi
  • Patent number: 11437298
    Abstract: An electronic module has a first substrate 11, an electronic element 13, 23 disposed on one side of the first substrate 11, a second substrate 21 disposed on one side of the electronic element 13, 23, a first coupling body 210 disposed between the first substrate 11 and the second substrate 21, a second coupling body 220 disposed between the first substrate 11 and the second substrate 21, and shorter than the first coupling body 210, and a sealing part 90 which seals at least the electronic element. The first coupling body 210 is not electrically connected to the electronic element. The second coupling body 220 is electrically connected to the electronic element 13, 23.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: September 6, 2022
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventors: Osamu Matsuzaki, Kosuke Ikeda
  • Patent number: 11435038
    Abstract: Lighting systems are described. A lighting system includes a first lead frame portion and a second lead frame portion. The first lead frame portion has at least a top surface, a bottom surface, and an opening. The second lead frame portion is within the opening of the first lead frame portion and has at least a top surface and a bottom surface. Light-emitting diode (LED) devices are each mechanically and electrically coupled to the top surface of the first lead frame portion and the top surface of the second lead frame portion. An electrically insulating and optically reflective material is disposed over exposed regions of the top surfaces of the first and second lead frame portions.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: September 6, 2022
    Assignee: Lumileds LLC
    Inventors: Peter Henri Bancken, Bas Fleskens
  • Patent number: 11437516
    Abstract: A semiconductor structure includes a gate structure disposed over a substrate, and a plurality of source/drain features disposed on the substrate and interposed by the gate structure. Each of the source/drain features includes a first doped source/drain region extended away from the substrate, and a second doped source/drain region disposed on top and side surfaces of the first doped source/drain region, in which a phosphorus doping concentration of the first doped source/drain region is lower than a doping concentration of the second doped source/drain region.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Szu-Chi Yang, Chih-Hsiang Huang
  • Patent number: 11424226
    Abstract: The invention relates to a light emitting device comprising: a support, at least two light-emitting elements at a top side of the support, first connection locations and a single second connection location at a bottom side of the support, wherein each light-emitting element comprises a first contact location and a second contact location at a side facing away from the support, each first contact location is connected to one of the first connection locations via a first connection, all of the second contact locations are connected to the second connection location via a second connection, the first connections run along an outer surface of the support, and the second connection runs through the support.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: August 23, 2022
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Seong Tak Koay, Adelene Geok Ling Ng, Chui Wai Chong, Teng Hai Chuah
  • Patent number: 11417808
    Abstract: A light emitting device includes: a resin package including first and second leads, and a resin part defining a recess defined by a lateral wall and an upward-facing surface, which includes an upper surface of a portion of each of the first lead, the second lead, and the resin part; and a light emitting element on the first lead. The resin part includes a holding resin portion between the first and second leads at the upward-facing surface, and a covering resin portion that covers a portion of the upper surface of the holding resin portion and a portion of an upper surface of at least one of the first and second leads. A portion of an upper surface of the holding resin portion is exposed from the covering resin portion, and is located on the same plane as the upper surfaces of the first and second leads.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: August 16, 2022
    Assignee: NICHIA CORPORATION
    Inventors: Kiyoshi Kayama, Shohei Mori, Akinobu Maeda
  • Patent number: 11414320
    Abstract: A method for producing a thin-film layer includes providing a layer stack on a carrier substrate, wherein the layer stack includes a carrier layer and a sacrificial layer, and wherein the sacrificial layer includes areas in which the carrier layer is exposed. The method includes providing the thin-film layer on the layer stack, such that the thin-film layer bears on the sacrificial layer and, in the areas of the sacrificial layer in which the carrier layer is exposed, against the carrier layer. The method includes at least partly removing the sacrificial layer from the thin-film layer in order to eliminate a contact between the thin-film layer and the sacrificial layer in some areas. The method also includes detaching the thin-film layer from the carrier layer.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: August 16, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Alfred Sigl, Wolfgang Friza, Stefan Geissler
  • Patent number: 11417543
    Abstract: A bonding apparatus includes a first holder, a second holder, an imaging unit and a moving device. The first holder is configured to hold a first substrate. The second holder is disposed to face the first holder and configured to hold a second substrate to be bonded to the first substrate. The imaging unit includes a first imaging device configured to image a first alignment mark formed on a surface of the first substrate facing the second substrate and a second imaging device configured to image a second alignment mark formed on a surface of the second substrate facing the first substrate. The moving device is configured to move the imaging unit in a first direction and a second direction intersecting with the first direction within a plan region between the first holder and the second holder.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: August 16, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshitaka Otsuka, Munehisa Kodama, Yutaka Yamasaki
  • Patent number: 11417804
    Abstract: The light emitting device package disclosed in the embodiment of the invention includes first and second frames; a body disposed between the first and second frames; and a light emitting devices disposed on the first and second frames. The first frame includes a first end portion adjacent to the second frame, and the second frame includes a second end portion adjacent to the first frame and facing the first end portion, the first end portion includes a first protrusion protruding toward the second frame, and the second end portion includes a second protrusion protruding toward the first frame. The light emitting device includes first and second bonding portions disposed on the first and second protrusions. The body includes first and second reflective portions extending toward both sides of the first protrusion toward the first frame, and third and fourth reflective portions extending toward both sides of the second protrusion toward the second frame.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: August 16, 2022
    Assignee: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
    Inventors: Young Shin Kim, Soon Yong Kang, Sung Min Kong, Ju Hyeon Oh
  • Patent number: 11417645
    Abstract: An electrostatic discharge protection structure includes a laterally diffused metal oxide semiconductor (LDMOS) device. The LDMOS device includes an embedded bipolar junction transistor. A gate, a source, a buried layer lead-out area, and a substrate lead-out area of the LDMOS device are grounded. A drain and a body region lead-out area of the LDMOS device are electrically connected to a pad input/output terminal. In an embodiment, the embedded bipolar junction transistor includes a PNP transistor operative to transmit a reverse electrostatic discharge current. An N+ drain, a gate, an N+ source, and a P+ substrate lead-out area form a grounded-gate NMOS (GGNMOS) operative to transmit a forward electrostatic discharge current.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: August 16, 2022
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Zhenghao Gan
  • Patent number: 11411085
    Abstract: Methods of fabricating a semiconductor structure comprise forming an opening through a stack of alternating tier dielectric materials and tier control gate materials, and laterally removing a portion of each of the tier control gate materials to form control gate recesses. A charge blocking material comprising a charge trapping portion is formed on exposed surfaces of the tier dielectric materials and tier control gate materials in the opening. The control gate recesses are filled with a charge storage material. The method further comprises removing the charge trapping portion of the charge blocking material disposed horizontally between the charge storage material and an adjacent tier dielectric material to produce air gaps between the charge storage material and the adjacent tier dielectric material. The air gaps may be substantially filled with dielectric material or conductive material. Also disclosed are semiconductor structures obtained from such methods.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: August 9, 2022
    Assignee: Micron Technology, Inc.
    Inventor: John D. Hopkins
  • Patent number: 11410890
    Abstract: A method includes providing a p-type S/D epitaxial feature and an n-type source/drain (S/D) epitaxial feature, forming a semiconductor material layer over the n-type S/D epitaxial feature and the p-type S/D epitaxial feature, processing the semiconductor material layer with a germanium-containing gas, where the processing of the semiconductor material layer forms a germanium-containing layer over the semiconductor material layer, etching the germanium-containing layer, where the etching of the germanium-containing layer removes the germanium-containing layer formed over the n-type S/D epitaxial feature and the semiconductor material layer formed over the p-type S/D epitaxial feature, and forming a first S/D contact over the semiconductor material layer remaining over the n-type S/D epitaxial feature and a second S/D contact over the p-type S/D epitaxial feature. The semiconductor material layer may have a composition similar to that of the n-type S/D epitaxial feature.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: August 9, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ding-Kang Shih, Pang-Yen Tsai
  • Patent number: 11404551
    Abstract: The present disclosure provides a transistor, a transistor forming method thereof, and a semiconductor device. The transistor forming method comprises providing a substrate, the substrate comprising a first region for forming a source region and a second region for forming a drain region; forming a gate groove in the substrate to separate the first region and the second region, a part of the substrate along the bottom of the gate groove being used for constituting an embedded channel region of a transistor; forming a gate dielectric layer on the gate groove of the substrate to cover the embedded channel region and to extend to cover a side of the first region and a side of the second region in the gate groove; and forming a gate conductive layer on the gate dielectric layer of the substrate and in the gate groove.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: August 2, 2022
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Ning Li
  • Patent number: 11404618
    Abstract: A light-emitting device package according to one embodiment comprises: a body including a through-hole formed in an upper surface and a lower surface; a light-emitting device arranged on the upper surface of the body and including first and second bonding units spaced apart from each other; and first and second metal units arranged so as to be spaced apart from each other on the rear surface of the body, wherein a partial area of each of the first and second bonding units overlaps with the through-hole in a vertical direction, the first and second metal units respectively includes first and second extension portions extending to the through-hole; the first and second extension portions is electrically connected to the first and second bonding units, respectively; and the first and second extension portions face each other within the through-hole.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: August 2, 2022
    Assignee: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
    Inventors: Ki Seok Kim, Chang Man Lim, Won Jung Kim
  • Patent number: 11393960
    Abstract: A semiconductor light-emitting device includes a substrate, a semiconductor light-emitting element, and a resin member. The substrate includes a base member and a conductive part. The semiconductor light-emitting element is supported on the substrate. The resin member covers at least a portion of the substrate. The base member has a front surface and a back surface that face opposite to each other in a thickness direction. The conductive part includes a front portion formed on the front surface. The semiconductor light-emitting element is mounted on the front portion. The resin member includes a frame-shaped portion surrounding the semiconductor light-emitting element as viewed in the thickness direction, and a front-surface covering portion connected to the frame-shaped portion and covering a portion of the front surface of the base member that is exposed from the front portion.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: July 19, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Tomoichiro Toyama, Ryo Kittaka
  • Patent number: 11393962
    Abstract: An optoelectronic semiconductor component may include a housing having a recess, and a chip carrier which is a part of the housing. The chip carrier may have a first fastening side and an upper side. The optoelectronic semiconductor chip may be mounted on the upper side in the recess. First electrical contact pads for external electrical contacting may be located on the first fastening side. Furthermore, second electrical contact pads for external electrical contacting may be located on a second fastening side, opposite to the first fastening side, of the housing. First and second electrical contact pads electrically assigned to one another may be electrically short-circuited so that the semiconductor component can be electrically contacted by the first or by the second fastening side.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: July 19, 2022
    Assignee: OSRAM OLED GMBH
    Inventors: Daniel Richter, Sven Weber-Rabsilber
  • Patent number: 11380819
    Abstract: A micro light emitting diode including an epitaxial structure and two electrodes is provided. The epitaxial structure includes a first surface, a second surface and a side surface. The first surface is opposite to the second surface, and the side surface is connected to the first surface and the second surface. The side surface includes a first portion and a second portion. The first portion is connected to the second portion to form a turning position. A width of the epitaxial structure gradually increases from the first surface to the turning position and gradually decreases from the turning position to the second surface. The two electrodes are disposed on the epitaxial structure and are electrically connected to the epitaxial structure. A micro light emitting diode device substrate adopting the micro light emitting diode is also provided.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: July 5, 2022
    Assignee: PlayNitride Display Co., Ltd.
    Inventors: Chih-Ling Wu, Yi-Min Su, Yen-Yeh Chen
  • Patent number: 11380827
    Abstract: Provided are a Light Emitting Diode (LED) device and a backlight module. The LED device includes a substrate, a chip, an encapsulation structure and a top reflective shielding layer; the chip is disposed on the substrate; the encapsulation structure covers the substrate and covers the chip; and the top reflective shielding layer is disposed on the encapsulation structure and located at a central position of an upper surface of the encapsulation structure, and covers a part of the upper surface of the encapsulation structure.
    Type: Grant
    Filed: June 23, 2020
    Date of Patent: July 5, 2022
    Assignee: FOSHAN NATIONSTAR OPTOELECTRONICS CO., LTD
    Inventors: Fuhai Li, Penghui Dong, Dongzi Chen, Zhiguo Xie, Quan Xie