Patents Examined by Margaret B Hayes
  • Patent number: 12101933
    Abstract: A semiconductor device that can be downsized more than ever before is provided. A semiconductor device 10 includes: an insulating layer 21 provided on an upper side of a substrate 20; a conductor 110 provided within the insulating layer 21; a conductor 120 provided within the insulating layer 21 and facing the conductor 110 in a first direction parallel with a surface of the substrate 20; and an insulating film 130 provided between the conductor 110 and the conductor 120. A thickness of the insulating film 130 in the first direction is smaller than both of a thickness of the conductor 110 in the first direction and a thickness of the conductor 120 in the first direction. A relative permittivity of the insulating film 130 is higher than a relative permittivity of the insulating layer 21. The conductor 110 and the conductor 120 extend in a second direction intersecting the first direction and parallel with the substrate 20.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: September 24, 2024
    Assignee: Kioxia Corporation
    Inventor: Masato Shini
  • Patent number: 12036711
    Abstract: A plasticization device that plasticizes a material, includes: a drive motor; a rotor that is to be rotated by the drive motor and has a groove-forming surface in which a curved projection strip portion is formed from a peripheral edge of a circular central portion toward an outer periphery of the rotor; a barrel that faces the groove-forming surface and includes a communication hole at a position facing the central portion of the groove-forming surface; and a heating unit that heats the material supplied between the rotor and the barrel, the rotor includes a protrusion protruding from the central portion toward the communication hole, and 0.28?S2/S1?1.03??(1), wherein S1 is an area of the central portion and S2 is a maximum area of a cross section of the protrusion along the groove-forming surface.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: July 16, 2024
    Assignee: Seiko Epson Corporation
    Inventors: Riona Hayashi, Seiichiro Yamashita, Kenta Anegawa, Megumi Enari, Masashi Fuchii
  • Patent number: 12031236
    Abstract: Electrospinning (ES) produces fibers with small cross-sections and high surface area, making them ideal for a multitude of applications. Structures produced using ES methods exhibit a high surface-to-volume ratio, tunable porosity, and controllable composition. ES involves the delivery of a liquid or solid polymer to a spinneret, whereby, an initiated electric field pulls the polymer into micro to nano-scale fibers. Due to the multitude of applications for which polymer fibers can be used, it is desirable to provide an efficient and portable ES device that allows on-demand deposition of polymer materials. The invention that is subject of this patent application is a portable ES device that allows ideal deposition on a substrate regardless of whether that substrate is attached to high voltage or grounded, and regardless of whether or not there is a charged or grounded substrate behind the desired deposition surface.
    Type: Grant
    Filed: May 30, 2020
    Date of Patent: July 9, 2024
    Assignee: Montana Technological University
    Inventors: Jack L. Skinner, Emily A. Kooistra-Manning, Jessica M. Andriolo, Lane G. Huston
  • Patent number: 12035541
    Abstract: A selector device includes: a first electrode; a second electrode; a selector layer that is disposed between the first electrode and the second electrode; and a stacked film that is disposed in at least one of a portion between the first electrode and the selector layer and a portion between the second electrode and the selector layer, and includes a first layer including at least one first element selected from the group consisting of carbon and metal and not including nitrogen and a second layer including nitride of the first element. The first layer is in contact with the selector layer.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: July 9, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Gu Tianyi
  • Patent number: 12035528
    Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: July 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung Jun Shin, Hyun Mog Park, Joong Shik Shin
  • Patent number: 12029134
    Abstract: A semiconductor device including a substrate; a lower electrode on the substrate; a magnetic tunnel junction structure on the lower electrode, the magnetic tunnel junction structure including a pinned layer, a tunnel barrier layer, and a free layer which are sequentially stacked; an upper electrode on the magnetic tunnel junction structure; and an oxidation control layer between the free layer and the upper electrode, the oxidation control layer including at least one filter layer and at least one oxide layer, wherein the at least one filter layer includes MoCoFe.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: July 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sanghwan Park, Younghyun Kim, Jaehoon Kim, Heeju Shin, Sechung Oh
  • Patent number: 12029048
    Abstract: A resistive memory device includes: memory cells overlapping one another in a vertical direction within a cell array region and each including a switching element and a variable resistive element; first conductive lines each being connected to the switching element; a second conductive line connected to the variable resistive element and conductive pads arranged in a connection region and connected to respective one ends of the first conductive lines, respectively, and having different lengths in the second horizontal direction. A lower conductive pad from among the conductive pads includes a first portion covered by an upper conductive pad, and a second portion not covered by the upper conductive pad, and a thickness of each of the first and second portions in the vertical direction is greater than a thickness of each of the first conductive lines in the vertical direction.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: July 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyunmog Park, Jungyu Lee, Daehwan Kang, Sungho Eun
  • Patent number: 12016179
    Abstract: A memory device includes an alternating stack of insulating layers and control gate layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure containing a memory film and a vertical semiconductor channel located within the memory opening. The memory film contains a resonant tunneling barrier stack, a semiconductor barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the semiconductor barrier layer.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: June 18, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Peter Rabkin, Masaaki Higashitani
  • Patent number: 11986993
    Abstract: The disclosure relates to methods of forming three-dimensional (3D) polymeric articles and additive manufacturing apparatuses for the same. The methods include providing a polymeric solution comprising a polymer dissolved in a solvent; providing a non-solvent, wherein the solvent is miscible in the non-solvent, and the polymer is insoluble in the non-solvent; and injecting the polymeric solution into the non-solvent in a pre-determined 3D pattern to provide a 3D polymeric article.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: May 21, 2024
    Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Henry A. Sodano, Ruowen Tu, Ethan Cassidy Sprague
  • Patent number: 11985818
    Abstract: An anti-fuse device includes: a substrate; an anti-fuse gate, partially embedded in the substrate, a portion of the anti-fuse gate embedded in the substrate having one or more sharp corners; and an anti-fuse gate oxide layer, located between the anti-fuse gate and the substrate.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: May 14, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: ChihCheng Liu
  • Patent number: 11950518
    Abstract: A phase-change memory device and method of manufacturing the same, the memory device including: a substrate; a bottom electrode disposed over the substrate; a top electrode disposed over the bottom electrode; and a phase-change layer disposed between the top and bottom electrodes. The phase change layer includes a chalcogenide Ge—Sb—Te (GST) material that includes at least 30 at % Ge and that is doped with a dopant including N, Si, Sc, Ga, C, or any combination thereof.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Jau-Yi Wu
  • Patent number: 11946874
    Abstract: There is provided a method for producing a nitride semiconductor laminate in which a thin film is homoepitaxially grown on a substrate comprising group III nitride semiconductor crystals, the method including: homoepitaxially growing a thin film on a substrate, using the substrate in which a dislocation density on its main surface is 5×106 pieces/cm2 or less, a concentration of oxygen therein is less than 1×1017 at·cm?3, and a concentration of impurities therein other than n-type impurity is less than 1×1017 at ·cm?3; and inspecting a film quality of the thin film formed on the substrate, wherein in the inspection of the film quality, the film quality of the thin film is inspected by detecting a deviation of an amount of reflected light at a predetermined wavenumber determined in a range of 1,600 cm?1 or more and 1,700 cm?1 or less in a reflection spectrum obtained by irradiating the thin film on the substrate with infrared light, from an amount of reflected light at the predetermined wavenumber determined ac
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: April 2, 2024
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventor: Fumimasa Horikiri
  • Patent number: 11927478
    Abstract: In a light detection device, the light detection unit includes an APD, a plurality of temperature compensation diodes, and a terminal electrically connecting the APD and the plurality of temperature compensation diodes in parallel with each other. The plurality of temperature compensation diodes is configured to provide temperature compensation for the gain of the APD. The light detection unit has a light detection region and temperature detection regions. The APD is provided in the light detection region. The temperature detection regions are located around the light detection region. The plurality of temperature compensation diodes are provided in the temperature detection regions. The light detection region is interposed between the temperature detection region and the temperature detection region.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: March 12, 2024
    Assignee: HAMAMATSU PHOTONICS K.K.
    Inventor: Hironori Sonobe
  • Patent number: 11917930
    Abstract: A resistance change device of an embodiment includes: a first electrode; a second electrode; and a stack disposed between these electrodes, and including a first layer containing a resistance change material and a second layer in contact with the first layer. The resistance change material contains at least one of a first element such as Ge and a second element such as Sb, and at least one third element selected from Te, Se, S, and O. The second layer contains a crystal material containing at least one selected from a group consisting of a first material having a composition represented by (Ti,Zr,Hf)CoSb, (Zr,Hf)NiSn, or Fe(Nb,Zr,Hf)(Sb,Sn), a second material having a composition represented by Fe(V,Hf,W)(Al,Si), and a third material having a composition represented by Mg(Si,Ge,Sn).
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: February 27, 2024
    Assignee: Kioxia Corporation
    Inventors: Takao Kosaka, Hiroki Tokuhira
  • Patent number: 11917836
    Abstract: The invention provides a RRAM structure, which includes a substrate, a high voltage transistor, and a RRAM cell. The high voltage transistor includes a drift region, a gate structure, a source region, a drain region, and an isolation structure. The drift region is located in the substrate. The gate structure is located on the substrate and on a portion of the drift region. The source region and the drain region are located in the substrate on two sides of the gate structure. The drain region is located in the drift region. The isolation structure is located in the drift region and between the gate structure and the drain region. The RRAM cell includes a first electrode, a resistive switching layer, and a second electrode sequentially located on the drain region. The RRAM cell is electrically connected to the high voltage transistor.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: February 27, 2024
    Assignee: United Microelectronics Corp.
    Inventor: Zong-Han Lin
  • Patent number: 11911825
    Abstract: In an example, a method is described that includes building a first layer of a three-dimensional heterogeneous object in a first plurality of passes of an additive manufacturing system. An electronic component is inserted directly into the first layer. The electronic component is then fused to the first layer in a second plurality of passes of the additive manufacturing system.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: February 27, 2024
    Assignee: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.
    Inventors: Kristopher J. Erickson, David George, Sterling Chaffins, Lihua Zhao
  • Patent number: 11897194
    Abstract: A process for additive manufacturing of a thermoset resin fiber reinforced composite comprises depositing a fiber material along a path having a direction; heating the fiber material using a heater to generate a moving thermal gradient in the fiber material trailing the heater relative to the path direction; and dispensing a thermosetting polymer material on the heated fiber material at a trailing distance the from the heater along the path. The thermosetting polymer dynamically wicks into the fiber material along the thermal gradient in the path direction.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: February 13, 2024
    Assignee: University of Delaware
    Inventors: Kelvin Fu, Baohui Shi
  • Patent number: 11891724
    Abstract: An electrospinning apparatus for producing ultrafine fibers according to the present invention comprises: a cylindrical metal guide disposed to surround a hollow tube needle, which receives a charged solution and discharges the charged solution in the form of a filament, wherein a high voltage is applied to the cylindrical metal guide to control droplet stability of the charged solution; and a strip-shaped metal guide including a plurality of strip-shaped metal plates, which extend outward from the cylindrical metal guide and are radially arranged to control the direction of a charged filament, whereby discharge droplets of the charged solution are stably maintained, and the charged filament formed therefrom maintains a constant directionality with respect to a substrate, so that a uniform pattern having ultrafine fibers can be manufactured on a collection part.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: February 6, 2024
    Inventor: Jong-Su Park
  • Patent number: 11872733
    Abstract: A method of forming an implant includes: placing a scaffold having a plurality of pores formed therein in a mold part cavity of a mold cavity of a mold, the placed scaffold including at least one vent opening that accepts at least one mold insert post of the mold, the at least one vent opening and the at least one mold insert post forming a clearance therebetween; and injecting molding material into the mold cavity to fill the mold cavity and form the implant such that gas flows through the clearance without molding material flowing through the clearance during the injecting.
    Type: Grant
    Filed: May 4, 2021
    Date of Patent: January 16, 2024
    Assignee: SMed-TA/TD, LLC
    Inventors: Gregory C. Stalcup, Kreigh R. Williams
  • Patent number: 11872755
    Abstract: An additive manufacturing apparatus includes a supporting portion, a powder supplying portion, a flattening member, a curing portion, and a controller. The supporting portion is configured to detachably support a shaping stage. The powder supplying portion is configured to supply powder. The flattening member is configured to move in a scanning manner above the shaping stage attached to the supporting portion. The controller is configured to execute a measuring process of detecting inclination between a shaping surface of the shaping stage attached to the supporting portion and a trajectory plane of a trajectory of scanning movement of the flattening member, an adjustment process of adjusting an orientation of the shaping stage on a basis of a detection result of the measuring process such that a degree of parallel between the shaping surface and the trajectory plane increases, a powder layer formation process, and a curing process.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: January 16, 2024
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yoshiyuki Beniya, Kota Kiyohara, Hitoshi Murao