Patents Examined by Margaret D Klunk
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Patent number: 8658544Abstract: This invention relates to a method for texturing a silicon surface and silicon wafers made by the method, where the method comprises immersing the wafers in an alkaline solution at pH>10, and applying a potential difference between the wafer and a platinum electrode in the electrolyte in the range of +10 to +85 V.Type: GrantFiled: March 12, 2009Date of Patent: February 25, 2014Assignee: Norut Narvik ASInventors: Ingemar Olefjord, Timothy C. Lommasson
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Patent number: 8652970Abstract: A processing gas is introduced to remove an oxide film on the surface of a silicon substrate 5. F radicals are allowed to act on the surface of the silicon substrate to etch a silicon layer. Then, NH3 gas, N2 gas and NF3 gas are introduced, allowing NHxFy to act on the oxidized surface of the silicon substrate 5, thereby forming (NH4)2SiF6. The resulting (NH4)2SiF6 is sublimated to remove by-products (SiOF, SiOH) on the surface of the silicon substrate 5.Type: GrantFiled: March 24, 2010Date of Patent: February 18, 2014Assignee: Ulvac, Inc.Inventors: Yoshiyasu Tajima, Seiichi Takahashi, Kyuzo Nakamura
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Patent number: 8647985Abstract: Semiconductor material substrates are polished by a method including at least one polishing step A by means of which the substrate is polished on a polishing pad containing an abrasive material bonded in the polishing pad and a polishing agent solution is introduced between the substrate and the polishing pad during the polishing step; and at least one polishing step B by means of which the substrate is polished on a polishing pad containing an abrasive material-containing polishing pad and wherein a polishing agent slurry containing unbonded abrasive material is introduced between the substrate and the polishing pad during the polishing step.Type: GrantFiled: July 2, 2008Date of Patent: February 11, 2014Assignee: Siltronic AGInventors: Juergen Schwandner, Thomas Buschhardt, Roland Koppert, Georg Pietsch
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Patent number: 8628678Abstract: The invention relates to a method for in-line measuring the active KOH concentration in a KOH etching process in which process silicon hydroxide is produced by a reduction reaction according to the formula: 2K+ (aq.)+2OH? (aq.)+2H2O+Si?2K+ (aq.)+H2SiO42? (aq.)+2H2 (g). The total concentration of KOH bath is measured by using a refractometer and the measurement result is corrected by the estimated K2H2SiO4 concentration.Type: GrantFiled: October 11, 2006Date of Patent: January 14, 2014Assignee: Janesko OyInventor: Ville Voipio
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Patent number: 8617993Abstract: A method is provided for treating the surface of high aspect ratio nanostructures to help protect the delicate nanostructures during some of the rigorous processing involved in fabrication of semiconductor devices. A wafer containing high aspect ratio nanostructures is treated to make the surfaces of the nanostructures more hydrophobic. The treatment may include the application of a primer that chemically alters the surfaces of the nanostructures preventing them from getting damaged during subsequent wet clean processes. The wafer may then be further processed, for example a wet cleaning process followed by a drying process. The increased hydrophobicity of the nanostructures helps to reduce or prevent collapse of the nanostructures.Type: GrantFiled: February 1, 2010Date of Patent: December 31, 2013Assignee: Lam Research CorporationInventors: Amir A. Yasseri, Ji Zhu, Seokmin Yun, David S. L. Mui, Katrina Mikhaylichenko
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Patent number: 8568598Abstract: A manufacturing method of a tip type probe includes the steps of: forming on a substrate an etching mask of a shape similar to a shape of a top surface of a truncated pyramid; forming the truncated pyramid by subjecting the substrate to isotropic etching using the etching mask as a mask member; stopping the isotropic etching when an area of the top surface reaches an area capable of generating near-field light; and forming a metal film on at least some of the side surfaces of the truncated pyramid by allowing film forming particles to enter into a space between the etching mask and the side surfaces and adhere onto the truncated pyramid. The directivity of the film forming particles is controlled so that the metal film has a thickness that is reduced gradually from a bottom of the truncated pyramid toward the top surface.Type: GrantFiled: February 18, 2009Date of Patent: October 29, 2013Assignee: Seiko Instruments Inc.Inventors: Majung Park, Manabu Oumi
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Patent number: 8546269Abstract: Techniques for fabricating nanowire-based devices are provided. In one aspect, a method for fabricating a semiconductor device is provided comprising the following steps. A wafer is provided having a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer. Nanowires and pads are etched into the SOI layer to form a ladder-like structure wherein the pads are attached at opposite ends of the nanowires. The BOX layer is undercut beneath the nanowires. The nanowires and pads are contacted with an oxidizing gas to oxidize the silicon in the nanowires and pads under conditions that produce a ratio of a silicon consumption rate by oxidation on the nanowires to a silicon consumption rate by oxidation on the pads of from about 0.75 to about 1.25. An aspect ratio of width to thickness among all of the nanowires may be unified prior to contacting the nanowires and pads with the oxidizing gas.Type: GrantFiled: April 3, 2009Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: Tymon Barwicz, Guy Cohen, Lidija Sekaric, Jeffrey Sleight
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Patent number: 8529779Abstract: A method for producing surface features and an etch masking method. A combination is provided of a block copolymer and additional material. The block copolymer includes a first block of a first polymer covalently bonded to a second block of a second polymer. The additional material is miscible with the first polymer. A film is formed of the combination directly onto a surface of a first layer. Nanostructures of the additional material self-assemble within the first polymer block. The film of the combination and the first layer are etched. The nanostructures have an etch rate lower than an etch rate of the block copolymer and lower than an etch rate of the first layer. The film is removed and features remain on the surface of the first layer. Also included is an etch masking method where the nanostructures mask portions of the first layer from said etchant.Type: GrantFiled: March 28, 2008Date of Patent: September 10, 2013Assignee: International Business Machines CorporationInventors: Joy Cheng, Mark W. Hart, Hiroshi Ito, Ho-Cheol Kim, Robert Miller
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Patent number: 8530353Abstract: A method of manufacturing a SiC substrate which has a first principal surface and a second principal surface, includes the step of removing, by a vapor phase etching process, at least a portion of a work-affected layer which is formed by mechanical flattening or cutting on the first principal surface of the SiC substrate.Type: GrantFiled: June 3, 2011Date of Patent: September 10, 2013Assignee: Hitachi Metals, Ltd.Inventor: Taisuke Hirooka
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Patent number: 8513097Abstract: Disclosed is a plasma processing device that provides an object to be treated with plasma treatment. A wafer as an object to be treated, which is attached on the upper surface of adhesive sheet held by a holder frame, is mounted on a stage. In a vacuum chamber that covers the stage therein, plasma is generated, by which the wafer mounted on the stage undergoes plasma treatment. The plasma processing device contains a cover member made of dielectric material. During the plasma treatment on the wafer, the holder frame is covered with a cover member placed at a predetermined position above the stage, at the same time, the wafer is exposed from an opening formed in the center of the cover member.Type: GrantFiled: October 9, 2008Date of Patent: August 20, 2013Assignee: Panasonic CorporationInventor: Tetsuhiro Iwai
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Patent number: 8501584Abstract: The process comprises the following steps: a) a first element (3) or a plurality of said first elements (3) is/are machined in a first silicon wafer (1) keeping said elements (3) joined together via material bridges (5); b) step a) is repeated with a second silicon wafer (2) in order to machine a second element (4), differing in shape from that of the first element (3), or a plurality of said second elements (4); c) the first and second elements (3, 4) or the first and second wafers (1, 2) are applied, face to face, with the aid of positioning means (6, 7); d) the assembly formed in step c) undergoes oxidation; and e) the parts (10) are separated form the wafers (1, 2). Micromechanical timepiece parts obtained according to the process.Type: GrantFiled: November 1, 2007Date of Patent: August 6, 2013Assignee: ETA SA Manufacture Horlogère SuisseInventors: Philippe Marmy, Jean-Luc Helfer, Thierry Conus
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Patent number: 8501626Abstract: Methods for etching high-k material at high temperatures are provided. In one embodiment, a method etching high-k material on a substrate may include providing a substrate having a high-k material layer disposed thereon into an etch chamber, forming a plasma from an etching gas mixture including at least a halogen containing gas into the etch chamber, maintaining a temperature of an interior surface of the etch chamber in excess of about 100 degree Celsius while etching the high-k material layer in the presence of the plasma, and maintaining a substrate temperature between about 100 degree Celsius and about 250 degrees Celsius while etching the high-k material layer in the presence of the plasma.Type: GrantFiled: June 25, 2008Date of Patent: August 6, 2013Assignee: Applied Materials, Inc.Inventors: Wei Liu, Eiichi Matsusue, Meihua Shen, Shashank Deshmukh, Anh-Kiet Quang Phan, David Palagashvili, Michael D. Willwerth, Jong I. Shin, Barrett Finch, Yohei Kawase
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Patent number: 8496843Abstract: A method for chemical mechanical polishing of a substrate is provided, comprising: providing a substrate, wherein the substrate comprises polysilicon and at least one of silicon oxide and silicon nitride; providing a chemical mechanical polishing composition, comprising, as initial components: water; an abrasive; and an alkyl aryl polyether sulfonate compound, wherein the alkyl aryl polyether sulfonate compound has a hydrophobic portion having an alkyl group bound to an aryl ring and a nonionic acyclic hydrophilic portion having 4 to 100 carbon atoms; providing a chemical mechanical polishing pad with a polishing surface; moving the polishing surface relative to the substrate; dispensing the chemical mechanical polishing composition onto the polishing surface; and, abrading at least a portion of the substrate to polish the substrate; wherein at least some of the polysilicon is removed from the substrate; and, wherein at least some of the at least one of silicon oxide and silicon nitride is removed from the suType: GrantFiled: March 16, 2010Date of Patent: July 30, 2013Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.Inventors: Yi Guo, Zhendong Liu, Kancharla-Arun Kumar Reddy, Guangyun Zhang
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Patent number: 8491800Abstract: Embodiments of the present invention relate to systems and methods for designing and manufacturing hard masks used in the creation of patterned magnetic media and, more particularly, patterned magnetic recording media used in hard disk drives (e.g., bit patterned media (BPM)). In some embodiments, the hard mask incorporates at least one layer of Ta (tantalum) and at least one layer of C (carbon) and is used during ion implantation of a pattern onto magnetic media. The hard mask can be fabricated with a high aspect ratio to achieve small feature sizes while maintaining its effectiveness as a mask, is robust enough to withstand the ion implantation process, and can be removed after the ion implantation process with minimal damage to the magnetic media.Type: GrantFiled: March 25, 2011Date of Patent: July 23, 2013Assignee: WD Media, LLCInventor: Paul Dorsey
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Patent number: 8491804Abstract: A method of processing a substrate having a processing target layer and an organic film serving as a mask layer includes a mineralizing process of mineralizing the organic film. The mineralizing process includes an adsorption process for allowing a silicon-containing gas to be adsorbed onto a surface of the organic film; and an oxidation process for oxidizing the adsorbed silicon-containing gas to be converted into a silicon oxide film. A monovalent aminosilane is employed as the silicon-containing gas.Type: GrantFiled: March 11, 2010Date of Patent: July 23, 2013Assignee: Tokyo Electron LimitedInventors: Masato Kushibiki, Eiichi Nishimura
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Patent number: 8491808Abstract: A method for chemical mechanical polishing of a substrate is provided, comprising: providing a substrate, wherein the substrate comprises polysilicon, silicon oxide and silicon nitride; providing a chemical mechanical polishing composition, comprising, as initial components: water; an abrasive; an alkyl aryl polyether sulfonate compound, wherein the alkyl aryl polyether sulfonate compound has a hydrophobic portion having an alkyl group bound to an aryl ring and a nonionic acyclic hydrophilic portion having 4 to 100 carbon atoms; and a substance according to formula I wherein each of R1, R2, R3, R4, R5, R6 and R7 is a bridging group having a formula —(CH2)n—, wherein n is an integer selected from 1 to 10; providing a chemical mechanical polishing pad with a polishing surface; moving the polishing surface relative to the substrate; dispensing the chemical mechanical polishing composition onto the polishing surface; and, abrading at least a portion of the substrate to polish the substrate; wherein at least sType: GrantFiled: March 16, 2010Date of Patent: July 23, 2013Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.Inventors: Yi Guo, Zhendong Liu, Kancharla-Arun Kumar Reddy, Guangyun Zhang
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Patent number: 8492277Abstract: A method for chemical mechanical polishing of a substrate is provided, comprising: providing a substrate, wherein the substrate comprises polysilicon and at least one of silicon oxide and silicon nitride; providing a chemical mechanical polishing composition, comprising, as initial components: water; an abrasive; and an acyclic organosulfonic acid compound, wherein the acyclic organosulfonic acid compound has an acyclic hydrophobic portion having 6 to 30 carbon atoms and a nonionic acyclic hydrophilic portion having 10 to 300 carbon atoms; providing a chemical mechanical polishing pad with a polishing surface; moving the polishing surface relative to the substrate; dispensing the chemical mechanical polishing composition onto the polishing surface; and, abrading at least a portion of the substrate to polish the substrate; wherein at least some of the polysilicon is removed from the substrate; and, wherein at least some of the at least one of silicon oxide and silicon nitride is removed from the substrate.Type: GrantFiled: March 16, 2010Date of Patent: July 23, 2013Assignee: Rohm and Haas Electronic Materials CMP Holdings, IncInventors: Yi Guo, Zhendong Liu, Kancharla-Arun Kumar Reddy, Guangyun Zhang
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Patent number: 8435902Abstract: A method of etching silicon oxide from a narrow trench and a wide trench (or open area) is described which allows the etch in the wide trench to progress further than the etch in the narrow trench. The method includes two dry etch cycles. The first dry etch cycle involves a low intensity or abbreviated sublimation step which leaves solid residue in the narrow trench. The remaining solid residue inhibits etch progress in the narrow trench during the second dry etch cycle allowing the etch in the wide trench to overtake the etch in the narrow trench.Type: GrantFiled: December 2, 2010Date of Patent: May 7, 2013Assignee: Applied Materials, Inc.Inventors: Jing Tang, Nitin Ingle, Dongqing Yang, Shankar Venkataraman
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Patent number: 8377320Abstract: A method of forming an undercut microstructure includes: forming an etch mask on a top surface of a substrate; forming, on a top surface of the etch mask, an ion implantation mask having a top surface that is smaller than the top surface of the etch mask and that does not extend beyond the top surface of the etch mask; ion implanting the substrate in the presence of the etch mask and the ion implantation mask so that a damaged region is generated at a depth below an area of the surface that is not masked by the ion implantation mask; and etching the surface of the substrate until the damaged region is removed.Type: GrantFiled: July 23, 2010Date of Patent: February 19, 2013Assignee: National Taipei University of TechnologyInventors: Tzyy-Jiann Wang, Yueh-Hsun Tsou
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Patent number: 8366953Abstract: A plasma cleaning method is performed in a plasma CVD apparatus for depositing a silicon nitride film on a surface of a target substrate, and includes a stage (S1) of supplying a cleaning gas containing NF3 gas into a process container, thereby removing extraneous deposits formed on portions inside the process container; a stage (S2) of supplying a gas containing hydrogen gas into the process container and generating plasma thereof, thereby removing residual fluorine inside the process container; and a stage (S3) of supplying a gas containing a rare gas into the process container and generating plasma thereof, thereby removing residual hydrogen inside the process container.Type: GrantFiled: September 18, 2007Date of Patent: February 5, 2013Assignee: Tokyo Electron LimitedInventors: Masayuki Kohno, Tatsuo Nishita, Toshio Nakanishi