Abstract: A charge pump includes a plurality of stages connected in series between a reference potential and an output terminal of the charge pump. The plurality of stages includes a first group of stages, proximate to the reference potential, and a second group of stages proximate to the output terminal of the charge pump. Each stage of the first group includes a pass-transistor with first and second terminals respectively connected to an input and an output of the stage, and a first capacitor with a first plate connected to the output of the stage and a second plate driven by a digital signal switching between the reference voltage and a positive voltage. Each stage of the second group includes a junction diode having a first electrode connected to an input of the stage and a second electrode connected to an output of the stage, and a second capacitor having a first plate connected to the output of the stage and a second plate driven by a digital signal switching between the reference voltage and the voltage supply.

Abstract: Minimal headroom, minimal area, multi-terminal current steering circuits for steering a current from a current source to any one of a plurality of outputs. The steering circuit provides controls to individual steering transistors so as to turn on the selected one of the plurality of steering transistors responsive to steering control signals. Minimal headroom is required, and beta dependent errors in the current output are minimized, by steering the current source through only a single transistor to the selected output. This also minimizes chip area. Alternate embodiments are disclosed and described.

Abstract: An interface output stage includes a pull-up circuit and a pull-down circuit connected to a positive power supply signal line having a first voltage, an output signal line having an output voltage and a negative power supply signal line having a second voltage. The pull-up circuit includes a single output transistor and a body snatcher circuit, both interconnected between the positive power supply signal line and the output signal line. The body snatcher circuit ties the bodies of the output transistor and the transistors forming the body snatcher circuit to either the first voltage or the output voltage. The pull-down circuit is designed generally similar to the pull-up circuit to tie bodies of its transistors to either the output voltage or the second voltage.

Abstract: This circuit includes an output stage consisting of a current source SCE 52 and a current sink SNK 51 having an identical construction. A reference signal is applied to a D-type flipflop 40A and a local oscillator signal is applied to another flipflop 40B of the same type. The output 28 (27) of the flipflop 40A (40B) triggers a control circuit 30A (30B) whose output C-SCE (C-SNK) controls the current source SCE (SNK). The inputs of a logic gate 60 are connected to the control circuits 30A, 30B, and the gate supplies an inactive state reset signal to the flipflops 40A and 40B and the control circuits 30. Bias voltages which are common for the control circuits are generated by a circuit 20 which also fixes the elementary output current of the charge pump.

Abstract: A novel PNP driven NMOS (PDNMOS) protection scheme is provided for advanced nonsilicide/silicide submicron CMOS processes. The emitter of a PNP transistor and the drain of protection NMOS device are connected to an I/O pad for which ESD protection is provided by the PDNMOS. The collector of the PNP transistor and the gate of the protection NMOS transistor are connected to ground through a resistor. The source of the protection NMOS transistor is grounded. The base of the PNP transistor is connected to either a capacitor or the parasitic capacitor of the integrated circuit.

Abstract: A semiconductor device comprises an MOS transistor, as a capacitive element, formed at the surface of a semiconductor substrate. A first power supply interconnection, above the substrate, applies a first power supply potential to the source and drain of the transistor. A second power supply interconnection, above the first interconnection, applies a second potential to the gate of the transistor. A third power supply interconnection is formed above, in parallel with and connected to the second power supply interconnection. An externally sourced potential is down-converted to be applied appropriately to the first, second and third power supply interconnections. This configuration achieves a semiconductor device that is less susceptible to power supply noise.

Abstract: A circuit for generating a reference potential includes a first transistor having an emitter connected to a ground potential, a base, and a collector connected to the base; a second transistor having a base connected to the base of the first transistor; a first resistor connected between the collector of the first transistor and an output terminal outputting the reference potential; a second resistor connected between the collector of the second transistor and the output terminal; a third resistor connected between the emitter of the second transistor and ground potential; a third transistor having a base connected to the collector of the second transistor, and an emitter connected to the ground potential; a fourth transistor having a collector connected to a supply potential, an emitter connected to the output terminal, and a base connected to the collector of the third transistor; a first current source connected between the base and the collector of the fourth transistor; and a second current source connec

Abstract: An auto mode selector for a semiconductor memory device having a reference voltage selection switching circuit connected between a reference voltage pin and an internal reference voltage terminal, for selecting one of CTT and LVTTL in response to a reference voltage selection signal. The auto mode selector further includes an input leakage current controller for allowing current to flow through a resistor between a supply voltage source and the reference voltage pin only for a predetermined time period in response to an input leakage current control signal from an input leakage current control signal generator. According to the present invention, the amount of input leakage current and standby current can be reduced.

Abstract: A method for reducing the current consumption of a reference voltage circuit while a synchronous DRAM is in standby power-down mode is provided. The reference voltage is stored on a capacitor within the DRAM circuit. The reference voltage circuit is selectively disconnected from, and reconnected to the Vref-node at predetermined time intervals during a power down mode, in order to ensure leakage compensation. When the power down mode exceeds a predetermined time, the reference voltage circuit is disabled to further reduce the current consumption.

Abstract: The Vpp generator for use in a dynamic random access memory has a pump circuit and a voltage regulator. The voltage regulator controls the pump circuit such that the pumped up voltage has a maximum predetermined value. The prior art Vpp regulator sets the pumped up voltage, Vpp, to approximately a supply voltage, Vcc, plus the threshold voltage of a memory cell access transistor. This level becomes very high when the supply voltage, Vcc, is high and may overstress the devices. The present invention regulates the pumped up voltage, Vpp, at a substantially constant voltage level for high supply voltages. This level is safe and will not cause overstress.

Abstract: An input/output voltage detection type substrate voltage generation circuit that of effectively prevents the electric potential of the substrate from being increased by varying the driving capability of a substrate voltage generation circuit. The input/output voltage detection type substrate voltage generation circuit preferably varies the driving capability by detecting an input electric potential of a data input/output terminal. The circuit includes a variable period type oscillator for receiving first, second and third signals as inputs to varying periods of the oscillator and a charge pump for pumping an electric charge to the substrate in accordance with a driving signal output from the variable period type oscillator and based on the variable period of the oscillator.

Abstract: The present invention provides a power amplifier operating with a single power supply. The amplifier includes at least one depletion-mode FET for amplifying an ac signal and a negative voltage generator for providing a bias to the FET. Preferably the amplifier further includes a negative voltage regulator to provide a regulated bias to bias the FET for a class A, AB or B operation. The negative generator includes a multivibrator for producing two clock signals and a charge pump which receives the clock signals and produces a negative voltage. Advantageously the negative voltage is provided as a low reference potential to the multivibrator so that the clock signals it produced include a negative voltage period, which enables the charge pump to operate in a power efficient manner.

Abstract: A voltage boost circuit having dual voltage outputs and a single input receives a DC voltage from an external source. The input voltage is boosted to provide a constant voltage at the first output at a level higher than the voltage input and to provide a constant voltage output at the second output. A switch is coupled to the output of the inductor for controlling the current flow to the second output.

Abstract: A first comparison circuit compares an internally generated clock signal with a reference signal and produces a first error signal in response to timing differences between rising edges of the clock signal and the reference signal. A second comparison circuit compares the internally generated clock signal with the reference signal and produces a second error signal in response to timing differences between falling edges of the clock signal and the reference signal. The first and second error signals are applied to control inputs of a phase shifter chain to control delay in each stage to reduce the timing error with respect to each edge.

Abstract: Selected transistors in a charge pump circuit have their associated well regions tied to a capacitor electrode. As a result, the body effect in these devices is reduced, and, consequently, the threshold voltage is reduced as well. With a lower threshold voltage, these transistors allow the charge pump to quickly generate a voltage higher than the positive power supply voltage or a negative substrate bias voltage. In addition, the metal-insulator-semiconductor (MIS) capacitors in the charge pump preferably have their source/drain regions tied to an associated well region, thereby shorting the source/drain/well region junction. Thus, parasitic capacitances associated with these MIS capacitors is significantly reduced, further increasing the speed of the charge pump circuit.

Abstract: An integrating circuit internally included in a semiconductor device includes a constant voltage circuit 11 for generating a predetermined constant voltage VREF, and a voltage-to-current converting circuit 12 for converting the voltage VREF into a constant current I0, which is supplied to a capacitor 15 externally connected to a connection terminal CPT. In order to detect an integral potential charged in the capacitor 15, a voltage comparator 14 having one input connected to the capacitor connection terminal CPT and the other input connected to an input terminal IN for receiving a signal VIN to be measured, inverts its output voltage when both the input voltages becomes consistent with each other. The integrating circuit also includes a switching circuit 13 having an input connected to an output terminal of the constant voltage circuit 11, an output connected to the capacitor connection terminal CPT.

Abstract: A selectable low power signal line (10) is provided that includes a driver circuit (12) connected to receive an input signal for transmission and to receive a mode select signal (SELECT). The driver circuit (12) has a low power mode and a full power mode selectable responsive to the mode select signal (SELECT). The driver circuit (12) is operable, when in the full power mode, to drive an output signal at a full swing of the input signal. When in the low power mode, the driver circuit (12) is operable to drive the output signal at a fraction of the full swing of the input signal. A physical signal line (14) is connected to receive the output signal of the driver circuit (12) and to carry the output signal. A receiver circuit (16) is connected to receive the signal on the physical signal line (14) and is also connected to receive the mode select signal (SELECT). The receiver circuit (16) has a low power and full power mode selectable responsive to the mode select signal (SELECT).

Abstract: A converter for providing an electrical signal according to the status of a light spot applied thereto, comprises: a sensor for sensing the light spot and generating a position current according to the position of the light spot sensed thereat; and an operating circuit for providing the sensor with an operating current when the light spot is sensed by the sensor and for outputting a status current corresponding to the operating current. The sensor comprises two electrodes each providing a current with magnitude determined according to the distance between it and the position of the light spot sensed thereat. The position current is obtained by subtracting the first electrode current from the second electrode current.

Abstract: A CMOS level converter including two CMOS inverter that are complimentary coupled with each other. Each of the CMOS inverter includes two MOS transistors and is coupled between a source voltage and a ground potential in series. When an input signal begins to change from a low level to a high level, one of the MOS transistors in an input side CMOS inverter is turned off, and the inverter is coupled through a diode to the ground potential. As the input level rises gradually, on the input side inverter, due to a high level output from an output side inverter, the MOS transistor turns on. As a consequent, the output is set at the ground potential in the level conversion, even when the amplitude is insufficient.

Abstract: A current-mode sense amplifier includes a current mirror circuit having an input branch controlled by a current input signal to be sensed and an output branch connected to a capacitor. The output branch and gates of current mirror transistors are connected to transistors for precharge operation. The sense amplifier needs no reference current, provides a low component count and is noise resistant.