Abstract: Feedback pulse generators each have an input and an output, a first digital gating circuit, and a second digital gating circuit. The first digital gating circuit is coupled between the input and the output of the pulse generator, and is responsive to an input signal from an external source changing from a first logic state to a second logic state that is received at a first input thereof for initiating a pulse at the output of the pulse generator.

Abstract: A divide-by-4/5 counter includes a half transparent register, a domino logic, a buffer, a divide-by-4 counter and a control circuit. The half transparent register includes first, second, and third NMOS and PMOS transistors and first and second inverters. The domino logic includes fourth PMOS and NMOS transistors and first and second switches. The buffer is connected to a drain of the fourth PMOS transistor for out putting a reference clock signal. The divide-by-4 counter includes two divide-by-2 counters to obtain a divide-by-2 clock signal and an output clock signal. The control circuit is connected to a control terminal of the second switch for outputting a control signal of the domino logic according to the divide-by-2 clock signal, the output clock signal and a divide-by-4/5 control signal.

Abstract: A reference voltage generating circuit includes a constant current circuit, a current mirror circuit, and a load resistor. The constant current circuit generates a constant current proportional to a thermal electromotive force. The current mirror circuit uses the constant current generated by the constant current circuit as a reference current. The load resistor converts the output current of the current mirror circuit into a voltage.

Abstract: A voltage divider is protected from current paths created by parasitic devices. The voltage divider includes a first string of diode-connected MOS transistors and a second string of diode-connected MOS transistors. A substrate bias terminal of each transistor in the first string is coupled to a substrate bias terminal of a corresponding transistor in the second string. The first string of transistors provides an output voltage which is protected from current paths created by parasitic devices.

Abstract: A first periodic pulse is rectified to generate an internal voltage by a charge pump circuit. A level detector is provided for detecting whether or not the internal voltage reaches a desired level. The charge pump circuit is controlled by a controller in accordance with the detection signal so that the internal voltage may take the desired level. A switch element switched by a second periodic pulse is provided in the current path of the level detector. A leakage current path for allowing a lower electric current than the electric current to flow through the former current path is provided between the output terminal of the charge pump circuit and a predetermined power supply terminal.

Abstract: The disclosure is an operation control circuit of a power supply unit in a memory device which outputs a given operation control signal used for supplying a power supply voltage when a main control signal of the memory device is operating and additionally outputs the operation control signal in response to a sub control signal driven when the main control signal does not operate.

Abstract: In order to reduce power consumption of the electronic device while it is inactive, the main switch 32 is shifted to the non-conductive state when the electronic device driven by the battery is stopped and the actuating signal decreases below a predetermined voltage, the actuating signal representing the state where the device is in operation. Thus, the power supplied to the control circuit or the like of the electronic device from the battery becomes zero, should a leak current or the like is ignored, and the power consumption can be reduced. In order to start the electronic device, the switch 34 is turned on and the main switch 32 is forced to the conductive state. That is, when the electronic device is started and the actuating signal exceeds the predetermined voltage, the main switch 32 becomes conductive and the electronic device receives power from the battery. In this state, even if the switch 34 is opened, the main switch 32 still remains conductive unless the actuating signal is stopped.

Abstract: A circuit configuration for generating an output voltage which is boosted beyond a supply voltage includes a boosting capacitor that is connected through a p-channel MOS transistor to an output node. A control circuit ensures that first of all the boosting capacitor and the output node are precharged through the use of respective precharging transistors when the p-channel MOS transistor is turned on, and that subsequently, during a shifting phase, the gate terminal of the p-channel MOS transistor is held at a floating potential. This prevents the voltage present between the gate and the main current path terminals of the p-channel MOS transistor from becoming greater than the supply voltage.

Abstract: In a voltage comparator of the present invention, across a gate and a source of an amplifier transistor, a phase compensating capacitor and a first switch circuit are connected with each other in series, and a second switch circuit for short-circuiting the phase compensating capacitor is provided. The second switch circuit is turned on when the first switch circuit is turned off so as to (1) short-circuit the phase compensating capacitor and (2) discharge the phase compensating capacitor which has been charged while the first switch circuit was turned on. This permits to completely turn off the first switch circuit, and to prevent distortion of an output signal outputted from an output terminal, thereby preventing accumulation of unnecessary charges in the phase compensating capacitor.

Abstract: A bandgap reference circuit (60) provides a selectable bandgap reference voltage that is substantially insensitive to temperature variations of an operating reference circuit. A final curvature caused by a current (I.sub.2) in a temperature coefficient compensation transistor (40) is equal to a drift in a Vbe voltage of a transistor (18) having a negative temperature coefficient plus the drift in a Vbe voltage of a transistor (20) having a positive temperature coefficient minus the drift in a Vbe voltage of the temperature coefficient compensation transistor (40). The nonlinearity of the current (I.sub.2) in the temperature coefficient compensation transistor (40) is adjusted by selecting a compensating current and associated temperature coefficient for the compensating current (I.sub.0) to minimize the characteristic bow or curvature of the current (I.sub.2) in the temperature coefficient compensation transistor (40).

Abstract: An integrated circuit built-in type power delay circuit which is capable of supplying a stable supply power to each circuit of the integrated circuit by generating a supply power control signal voltage after a predetermined time. The circuit includes a receiving unit for receiving a supply voltage VDD and charging the same, a supplying unit for supplying a current, an inverting unit for inverting an output value from the charging unit, a switching unit controlled in accordance with an output value from the inverting unit for switching an output from the current supply unit, a current regenerating unit for receiving a control of the switching unit and discharging an output value from the charging unit, an electric potential value conversion unit controlled by an output value from the inverting unit for converting an output value from the charging unit into a low level, and a buffering unit for receiving an output value from the inverting unit for buffering the output value and outputting a non-inverted signal.

Abstract: A power-on detect circuit includes: a resistor divider having a first node, a second node coupled to ground, and a center tap; a bandgap circuit for providing a reference voltage; a differential amplifier having a first input for receiving the reference voltage, a second input coupled to the center tap of the bandgap reference voltage circuit, and an output for providing a power-on detect signal; and a suppression circuit for coupling the first node of the resistor divider to a source of supply voltage once the reference voltage substantially achieves a stable reference voltage level. The suppression circuit has an input for receiving a trigger voltage generated in the bandgap circuit, and an output coupled to the first node of the resistor divider.