Abstract: A technique for assigning addresses to modular units connected to a computer system expansion bus. A unique address is initially generated in a controller module attached to the expansion bus and is transferred to the first one of several serially coupled expansion modules. The first modules receives the unique address which now identifies that module and generates a new unique address from the received unique address. The new unique address is transferred to the next expansion module which uses the received address to identify itself. The steps are repeated until each expansion module has received a unique address to identify itself. In each module, a Read Only Memory (ROM) is used to receive the unique address from the previous module and to generate a new address for the next module.

Abstract: A latch transfers fetched opcode to PLA for execution at the earliest opportunity following execution of a prior single cycle opcode.

Abstract: A data driven processing system includes a mechanism for generating a data pair from a sequential input data stream by matching identifier fields. The pairing mechanism comprises a hash memory in which input data words to be paired are stored by using hashed addresses. If a hash collision occurs, the data word which caused the hash collision is transmitted to a counter-directional data loop which is used to generate a data pair. If an input data word is not paired after one pass through the data loop it is returned to the hash memory for another pairing operation. Use of both the hash memory and the counter-directional data loop reduces the required hash memory size and increases processing efficiency.

Abstract: In a sequence controller which is capable of debugging a program including a plurality of sequence programs, a program head code is provided in the program to identify respective sequence programs. In executing the program, the number of sequence programs which are executed is counted by detecting the program head codes associated therewith. Thus, sequence processing can be effected for a predetermined number of sequence programs by stopping the processing of the sequence when the count of the detected program head codes becomes equal to the predetermined number. In addition, it is possible to count only those sequence programs which satisfy a certain condition, such as sequence programs which require a particular operation or relate to a particular control element. In this way, debugging of the program is facilitated.

Abstract: A microcomputer selectively operable in a first mode or a second mode comprises a first read-only memory for storing a first program to be executed in the first mode, a second, programmable read-only memory for storing a second program to be executed in the second mode, an input circuit for inputting the second program to be written in the second read-only memory, an execution circuit for executing the first program or the second program, and a mode control circuit responsive to a mode selection signal for enabling execution of the first program when the mode selection signal designates the first mode and for enabling writing and execution of the second program when the mode selection signal designates the second mode.

Abstract: A method and circuitry for communicating both byte transfer I/O data and file transfer I/O data to an individual I/O module through an equipment chassis backplane in a programmable controller. The byte transfer data is real time I/O data representing the status of I/O devices on an industrial machine or process. The file transfer data includes fault diagnostic data concerning conditions of the I/O devices in addition to their ON or OFF state. The circuitry is integrated into a single integrated circuit. The methods and circuitry are applicable to two different modes of addressing, one mode being used by earlier programmable controller processors and adapters and the other mode being used by newly developed processors and adapters.

Abstract: In a data processing system employing virtual memory techniques and capable of performing a plurality of overlapping scalar and vector data processing operations, apparatus and method are provided to allow continuation of program execution after one or more vector load/store instructions, which refer to data values that are not currently in memory, receive page faults. At the occurrence of such a page fault, all instructions currently in execution are allowed to be completed, whereupon information summarizing the page fault condition is recorded in memory for use by the operating system software and a vector exception is generated. Operating system software responds to this exception, examines the fault information, causes the missing pages to be read into the main memory unit from the mass storage media, re-executes the exception producing vector instruction(s) and continues with the program execution.

Abstract: A Record Lock Processor is utilized in a multi-host data processing system to control the locking of Objects upon request of each of the multiple host data processors in non-conflicting manner. The Record Lock Processor has storage provisions which include a Lock List for storing bits that identify the Objects and bits that identify the requesting processor, a Queue List that stores entries that are formatted like the Lock List entry when a prior Lock List entry has been made for the same Object, and a Cache List for each processor that stores Cache List entries that identify each Object that is stored in the cache memories, each of which Cache List entries is associated with one of the requesting processors, wherein such Cache List entries include validity bits that identify whether each Object stored in a Cache List has a Valid or an Invalid status.

Abstract: A data management mechanism for a processor system provides for management of data with minimum data transfer between processes executing work requests. Each process has storage areas for storing data associated with work requests. The data is described with descriptor elements in the work requests which indicate the location and length of segments of the data. Data is transferred to a process only if it is required for execution of a work request. Further work requests can be generated by a process executing a work request which reference the data without the process actually receiving the data. The segments of data may reside in storage areas of different processors with the descriptor elements of a work request defining a logical data stream.

Abstract: A method for use in an interactive information handling system which manages a relatively large plurality of electronic documents for a plurality of end users in which an end user who is not the owner of a document, may request a delayed copy of the document to be furnished only at the time that the owner's copy of the document is to be deleted from the system. A Delayed Copy Request (DCR) is entered into the system interactively by the non-owner end user when a screen is displayed on the end user's terminal. This screen prompts the end user for the information required by the system to subsequently present to the end user document owner. At the time the document is to be deleted, the information is redisplayed to the document owner which allows the owner to decide if the request should be honored.

Abstract: A high speed search processor capable of performing a wide variety of search functions, including simple and complex searches, either within an entire text stream or within predefined fixed or sliding windows in the text stream. The processor is made up of multiple interconnected cells, each of which has a pattern register for storing part of a pattern to be searched for, a character register for storing a character of the data stream to be searched, a match register for storing a match value indicative of a match between the search pattern and the text stream, and match logic for modifying an incoming match value in accordance with conditions within the cell. The data stream and the search pattern are oppositely oriented, such that a first character of the search pattern is first encountered by a first character in the data stream, and the pattern is successively compared with an equal number of characters in the data stream as it is moved through the search pattern.

Abstract: An integrated priority network is provided for a bus architecture computing system of the type employing a M-Bus connected to a plurality of functional elements. Each functional element has its own integrated priority resolution network (IPRN) coupled to said M-Bus for activating its own unique individual priority request and for receiving all individual priority requests from all other functional elements. Each integrated priority resolution network unit is provided with a rotational priority circuit and a preemptive priority circuit connected in parallel and operable independently to produce a request granted signal. Logic circuits in each rotational priority circuit determine when an IPRN unit will be granted its priority request for access to said M-Bus and will block future requests from being activated to its IPRN unit until the other IPRN unit values in the rotational priority register of the rotational priority circuit have been granted access to said M-Bus.

Abstract: A microprocessor system employing an 80386 CPU and an 82385 cache controller has the capability of functioning with dynamic bus sizing (where the CPU interacts with devices which may or may not be 32-bits wide), as well as posted write capability. Unfortunately, the two capabilities have the possibility of an incompatibility if a write cycle is posted to a device which cannot transfer 32 bits on a single cycle. The present invention provides logic to overcome this incompatibility. An address decoder is provided to decode the tag portion of an address asserted on a CPU bus to determine if the asserted address is inside or outside a range of addresses which define cacheable devices. Any cacheable device is by definition 32 bits wide and therefore posted writes are allowed only to cacheable devices. Accordingly, the microcomputer system employing the invention posts write cycles to cacheable devices; write cycles to non-cacheable devices are inhibited from being posted.

Abstract: A local area network permits wireless transfer of digitized data among data processing machines in the interior of a building. The network includes a base station which may commonly be associated with shared network resources such as a host computer, print servers and file servers and a plurality of local stations each associated with a data processing machine such as a dumb terminal dependent on the host computer. The base station polls each local station to initiate a transmission of data to the base station. All data including request for data is transmitted as temporally spaced-apart packets spread spectrum modulated according to a pseudo-random noise code common to all stations and encoded onto an RF carrier which is common to all stations. The transmitted data packets include a synchronization code which permits proper spread spectrum decoding without loss of relevant data.

Abstract: In parallel processing computational apparatus, a switching network employing both routing switch elements and concentrator elements efficiently couples bit serial messages from a multiplicity of processors to a multiplicity of memory modules. The apparatus operates in a highly synchronous mode in which all processors issue memory requests only at essentially the same predetermined time within a frame interval encompassing a predetermined substantial number of clock periods. The routing switch elements and concentrator elements incorporate circuitry for comparing the addresses of requests which may be blocked at any element with requests which get through and, if the addresses are the same, returning the memory response to all processors seeking the same memory location.

Abstract: An IC card includes an addressable CPU having a memory space including a special area including a first plurality of memory addresses which are addressable with a short instruction word, first and second memories in which test and application programs are stored, respectively, a bus which connects the CPU and the first and second memories, a first selection circuit for forming a first memory mapping arrangement in which at least a portion of the first memory is superimposed on the special area, a second selection circuit for forming a second memory mapping arrangement in which at least a portion of the second memory is superimposed on the special area, a detection circuit for detecting the execution of the test program or the application program, and a changeover circuit arranged to selectively operate the first and second selection circuits according to the result of detection executed by the detection circuit.

Abstract: Within a data processing system, a control mechanism for supporting a data space without common segments in addition to traditional address spaces containing common segments. Logic for eliminating duplication of lookaside table entries for virtual addresses within shared segments, but not for identical virtual addresses within data address spaces is provided, as well as for overriding low address protection for store operations into data spaces. Thus, the entire virtual addressing range is available to programs wishing to use such data spaces for data isolation and data sharing.

Abstract: A data processing system has files stored on disks in a tree structure of directories and files. The system is operated to rapidly open files which have been recently opened or for which partial path information is available, by accessing a drive cache in main memory. The cache has entries chained in a tree structure which is then searched to provide the same information during the opening process as that information which would otherwise have to be gotten from a disk. When the cache is full, a new entry replaces the least recently used entry.

Abstract: Basic operation clock generators for effecting frequency division of the system clock are provided for respective ones of a plurality of processors, and the basic operation clock generators associated with respective processors are connected in cascade. The basic operation clock generator of the preceding stage produces a synchronization signal in response to each particular state of the basic operation clock signal and supplies the synchronization signal to a basic operation clock generator of a succeeding stage, and the basic operation clock generator of the succeeding stage establishes the initial state in the basic operation clock signal by using the synchronization signal supplied from the basic operation clock generator as a control signal, whereby the phases of basic operation clock signals of respective processors are matched to each other.

Abstract: A node for communicating with a plurality of other nodes in a computer, the node including logic circuitry for transmitting and receiving data at first and second logic levels. A default generator is connected to an arbiter and responds to a lack of request activity and the absence of a multi-cycle data transfer being performed on the bus and causes the bus to be driven to one of the first and second logic levels.