Abstract: A multiple format hand held label printer includes a processor, a memory, a keyboard, a thermal printer and an advance mechanism for a tape of successive labels carried on a substrate. The processor reads operator keyboard inputs and formats both machine readable bar code data and alphanumeric data for the printer. The printer is actuated to imprint such information on successive adhesive backed labels. In addition, the processor stores label print information and sequentially changes print indicia to meet particular requirements. The processor communicates with a system processor for coordinated inventory control, market study or other functions.

Abstract: In the conventional CPU, when an interruption occurs during execution of a stack control instruction, the interrupted stack control instruction is executed again beginning from the start, so that a stack memory address currently designated by the stack pointer does not match that corresponding to the start of the instruction execution, thus resulting in a program error. To overcome the above problem, at the start of information saving and/or return operation, a stack memory address stored in the first register so as to be read next is additionally stored in the second register. Although the above operation is executed on the basis of the stack memory address stored in the first register, in case an interrupt occurs, the stack memory address stored in the second register is set to the first register before executing again the interrupted stack control instruction.

Abstract: A multiprocessor computing system is disclosed which includes a system bus, a plurality of processing units and a plurality of synchronous input/output channel controllers. A plurality of priority lines each corresponding to a processing unit are provided through each input/output channel controller in order of priority. A synchronizing signal is generated at the same time in each input/output channel controller in response to the end of an address phase on the system bus. A latch is provided in the input/output controllers which responds to the synchronizing signal by storing the condition of the priority lines and whether an interrupt is pending. In response to a broadcast interrupt origin request instruction from a processing unit, all input/output channel controllers will respond at the same time but only the one with the priority interrupt for the requesting processing unit gives a non-zero response.

Abstract: A multiprocessor system in which the base module comprises 32 microcomputer modules and provides a possibility for expansion. The interprocessor exchange is realized by a four-stage interconnection network with cyclic structure, which comprises 16 communication nodes. To each communication node there are connected two microcomputer modules and its structure comprises multiplexers, priority logics, input buffers, commutator elements, local controllers, demultiplexers, address registers and digital comparators. The self-synchronizing interconnection network provides spiral routes for eliminating any deadlock, as well as their reservation, which determines the high reliability and good possibilities for fault-tolerance.

Abstract: Phrases in an input character string are registered in a table (phrase table), frequencies of occurrence of those phrases are counted and registered in the table, the phrases having high frequencies of occurrence are selected and macro codes therefor are determined, and those macro codes and the corresponding phrases are paired and registered in the macro table. A content of the macro table thus prepared may be displayed on a display screen. Thereafter, a user can enter a desired phrase by keying the corresponding macro code.