Abstract: The present invention provides a remote control system for a power supply, comprising: a display data channel (DDC); a first control circuit electrically connected to said DDC, coding and sending a control signal through said DDC to control said power supply; a second control circuit electrically connected to said DDC, receiving and decoding said control signal through said DDC to control said power supply.

Abstract: A power-managed server and method for managing power consumption is disclosed. According to one embodiment, a power-managed server data processing system is provided among a plurality of server data processing systems which comprises a power management communication port to communicatively couple the power-managed server data processing system to a power management server data processing system of the plurality of server data processing systems. The power-managed server data processing system of the described embodiment further comprises a system management processor coupled to the power management communication port which comprises power-managed logic configured to transmit power management data to the power management server data processing system and to receive a power management command utilizing the power management communication port. Moreover, the power management command is generated utilizing the power management data, and the power management data comprises power management capability data.

Abstract: A system and method to evade the power on self test during an operating system initiated reboot is disclosed. In one embodiment, a method for optimizing reboot process of a computer includes determining a status of a power on self test (POST) performed during a prior booting of the computer when an operating system (OS) initiated rebooting of the computer is triggered, loading information obtained during the POST of the prior booting of the computer into a basic input output system (BIOS) of the computer if the status of the POST performed during the prior booting of the computer indicates a success of the POST, and performing the rebooting of the computer using the information, wherein a subsequent POST associated with the rebooting of the computer is skipped during the rebooting of the computer.

Abstract: An integrated circuit (IC) chip containing a plurality of voltage islands containing corresponding functional blocks that can be selectively fenced, i.e., powered down, while saving the states of the corresponding inputs, and unfenced in order to manage power consumption of the chip. Each fencable functional block includes a power switch and state-saving circuitry for saving the state of the inputs to that functional block. A power modulation unit (PMU) generates fencing signals that control the power switches and state-saving circuitries so as to selectively fence the corresponding functional blocks. The PMU generates the fencing signals as a function of one or more operating arguments.

Abstract: A noise reduction method by implementing certain point-to-point delay is disclosed. In this regard a method is introduced comprising determining a frequency of a greatest noise on a high-speed data link when turning on a power delivery network, determining a delay time between a first port and a second port that minimizes the greatest noise, and turning on the second port after the delay time from turning on the first port. Other embodiments are also disclosed and claimed.

Abstract: The present invention is a system and method for precise absolute time event generation and capture. One embodiment of the present invention is a programmable hardware module for TTL pulse generation and capture in absolute time. The nominal accuracy of the programmable hardware module is 25 ns. The time reference is an on-board GPS (Global Positioning System) receiver. The hardware embodiment of the present invention can generate eight independently programmable outputs and capture the times on eight independently programmable inputs. An exemplary application for the present invention is triggering external light sources, and flash-lamp pumped lasers in particular, at specific times for calibration of cosmic-ray observatories. A software embodiment of the present invention is implemented in a Linux software device driver interface featuring an extensive set of user commands.

Abstract: In some embodiments, an apparatus includes processor cores, a smaller non-volatile memory, a larger non-volatile memory to hold an operating system, programs, and data for use by the processor cores. The apparatus also includes volatile memory to act as system memory for the processor cores, and power management logic to control at least some aspects of power management. In response to a power state change command, a system context is stored in the smaller non-volatile memory followed by the volatile memory losing power, and in response to a resume command, the volatile memory receives power and receives at least a portion of the system context from the smaller non-volatile memory. Other embodiments are described.

Abstract: A method of initializing a booting procedure of a mobile platform having a certain NAND flash memory. The method comprises sending (304) an initial read command sequence to the NAND flash memory and detecting (305) if the NAND flash memory is responsive to the read command sequence. If the NAND flash memory is responsive to the read command sequence the mobile platform will be configured (306) to interface with the NAND flash memory. If the NAND flash memory is not responsive to the initial read command sequence, the method further comprises sending (307) another read command sequence to the NAND flash memory. The another read command sequence is associated with the initially sent read command sequence. Next, it is detected (308) if the NAND flash memory is responsive to the another read command sequence, and if so the mobile platform will be configured (309) to interface with the NAND flash memory.

Abstract: A system and method for performing dynamic trimming. Specifically, the system comprises a clock for generating a reference clock signal. The reference clock signal comprises a first frequency that is a factor of a second frequency of a signal (e.g., data clock signal from DDR memory). A counter is coupled to the clock and generates a plurality of clock pulses based on pulses of the reference clock signal. The plurality of clock pulses is generated at a slower frequency from the first frequency for low power operation. A phase length detector is coupled to the counter and comprises a trimmer chain for detecting an average length of at least one of the generated plurality of clock pulses. A transformation module is coupled to the phase length detector for transforming the average length to a phase delay of the signal.

Abstract: The present invention provides a method and system for controlling leakage power consumption at a System on Chip (SoC) level during a normal run or a boot-up mode. The leakage power reduction is achieved by incorporating a central programmable controller in the SoC architecture and test structures of idle SoC peripherals to place them into an Absolute Minimum Power consumption state with respect to static and dynamic power.

Abstract: An information processing apparatus including: a first recording medium which stores a first program; a connection section which is capable of connecting with a second recording medium from outside; and a controller which determines, during BIOS boot-up operation, whether or not the connection section is connected with the second recording medium which stores predetermined authentication information, and if connected, boots a second program stored in the second recording medium, while if not connected, boots the first program stored in the first recording medium.

Abstract: An apparatus and method for managing a power-saving mode of a portable terminal are provided. The method includes when a application program is running, assigning a network traffic type of the application program with one of a class type selected from a plurality of predefined class types of a sleep mode, instructing a modem to operate in the sleep mode of the assigned class type, and operating the modem in the sleep mode of the assigned class type.

Abstract: Systems and methods are described for synchronizing an HVAC control system. A method, includes: a synchronization sequence including: reading a base time from an internal clock at a first time and saving the base time; measuring an elapsed time interval, from the first time to a second time, by counting an external clock using a frequency counter; and then resetting the internal clock to the base time plus the elapsed time.

Abstract: A computer system which includes a CPU for performing various processes by program control and storage elements which store at least one operating system and a BIOS, wherein upon starting a system, the CPU recognizes the system's own hardware configuration, and starts a selected one operating system stored in the storage elements in accordance with the recognized hardware configuration under the control of the BIOS.

Abstract: In one embodiment, an apparatus comprises one or more processors and a controller coupled to the processors. Each processor comprises at least one processor time stamp counter (TSC) and a first control unit configured to maintain the processor TSC. The controller comprises at least one controller TSC and a second control unit configured to maintain the controller TSC. The controller is configured to signal the processor responsive to determining that the processor TSC is out of synchronization with the controller TSC. In response to having been signalled that the processor TSC is out of synchronization, the processor is configured to resynchronize the processor TSC to the controller TSC before generating a result for a read TSC instruction. In response to having not been signalled that the processor TSC is out of synchronization, the processor is configured to generate the result responsive to the processor TSC without resynchronizing.

Abstract: An asynchronous data holding circuit including a source synchronizer which acquires an enable signal synchronized with a destination clock, in response to a rising or falling edge of the enable signal, acquires the other one of the rising or falling edge of the enable signal in synchronization with a source clock, and outputs the enable signal, a first data holding unit which holds a data signal from the source, in response to the enable signal from the source synchronizer and the source clock, a destination synchronizer which outputs the enable signal from the source synchronizer, in synchronization with the destination clock, and a second data holding unit which holds the data signal in the first data holding unit in response to the enable signal from the destination synchronizer and the destination clock, is provided.

Abstract: A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.

Abstract: A digital circuit system includes: a register, for receiving and registering digital data; an operation unit, for operating and generating resulting data according to the digital data registered in the first registering unit; a second register, for receiving and registering the resulting data; a multi-phase clock signal generating unit, for generating a plurality of reference clock signals having different phases with each other; a first selector, for selecting one of the reference clock signals to output a first clock signal to the first registering unit; and a second selector, for selecting another of the reference clock signals to output a second clock signal to the second registering unit.

Abstract: An engine unit and a control unit are connected via an interface. A power source supplies electric power to the interface. The engine unit is controlled based on a reference clock generated in the control unit and transmitted to the engine unit via the interface. Only when a voltage output from the power source to the interface is in the operating-voltage range, the clock generator sends the reference clock to the engine unit via the interface.

Abstract: Embodiments of the present disclosure provide a power-optimizing memory analyzer, a method of operating a power-optimizing memory analyzer and a memory system employing the analyzer or the method. In one embodiment, the power-optimizing memory analyzer is for use with an array of memory blocks and includes a task database configured to provide a parameter set corresponding to each of a set of tasks to be performed in a system. The power-optimizing memory analyzer also includes an allocation module configured to determine offline, a group of memory blocks in the array corresponding to the parameter set for each task and based on providing a power reduction for the array. The power-optimizing memory analyzer further includes a power profiling module configured to generate run-time power profiles of memory power states for each task allowing transparent and dynamic control of the memory power states while maintaining a required quality of service.