Abstract: An activation system is applied to a computer apparatus. An activation signal is received by the computer apparatus to implement a booting action. The system comprises an external power adapter and a detection unit. An external power is received by the external power adapter. The external power then is provided to the computer apparatus. Meanwhile, a power supply signal then is generated by the external power adapter. The power supply signal is detected by the detection unit. The activation signal is outputted by the detection unit after detecting the power supply signal, so as to boot the computer apparatus through the external power.

Abstract: In the method of determining a time offset estimate between a central node and a secondary node, the central node receives downlink and uplink timing information from a secondary node. The downlink and uplink timing information are measured based on a periodic timing scale. The downlink timing information represents timing information for communication between the central node and the secondary node, and the uplink timing information represents timing information for communication from the secondary node to the central node. The central node compensates the timing information for time wraparound, and determines the time offset estimate based on the compensated timing information.

Abstract: A double data rate interface in which the set-up interval is extended for a data path in which data is delayed relative to the other data path. Data is latched into a register comprised of mid cycle type latches, such as for example L2* latches. For example, if the delayed half of the data is not available until the second half of the double data rate cycle, the second half of the data is allowed to have a set-up interval around the mid cycle point while the on-chip timing logic launches the least delayed half of the data on the clock edge after it is set up, without waiting for the expiration of the set up interval of the delayed data.

Abstract: A Heart Beat System (HBS) enables both inertial navigation system (INS) technology and other sensors, e.g., laser radar (LIDAR) systems, cameras and the like to be precisely time-coupled. The result of this coupling enables microsecond control by the HBS to each sensor slave component. This synchronization enables the precise time of each sensor measurement to be known which in turn allows highly accurate world coordinates to be computed from each set of received date, e.g., laser pulses range data. Such precision results in 3-dimensional point cloud data with relative accuracies in the 5-10 cm range and absolute positioning accuracies in the sub 40 cm range. This precision further enables multiple sensors to be used simultaneously with outstanding registration which leads to fused 3D point cloud databases representing a more comprehensive urban scene. Finally, 3D data collected from subsequent missions can be used for precision change detection analysis.

Abstract: A system and method for switching digital circuit clock net driver without losing clock pulses is presented. A device uses glitchless clock selection logic, which includes an edge detector, to select a clock signal to provide to device circuitry based upon the device circuitry's performance requirements. When the rising edges of a first clock signal and a second clock signal align, the edge detector momentarily pulses a clock switch signal, which is used to clock in a clock selection signal to a multiplexer. As a result, when the clock selection signal is high, the device waits until the clock edges are aligned before switching clock signals.

Abstract: A method, system and computer-readable medium for managing the building of indexes are presented. In one embodiment, the method includes the steps of: initiating an index rebuilding process in a computer; detecting a “Power down” command for the computer; evaluating a progress level of the index rebuilding process; in response to the index rebuilding process exceeding a predetermined completion level, delaying the “Power down” command until the index rebuilding process is completed; and in response to the index rebuilding process being less than the predetermined completion level, aborting the index rebuilding process and executing the “Power down” command.

Abstract: An inverter control circuit is used to control a switch and a transformer in front of a light-emitting unit and then adjust the driving power for the light-emitting unit and modify the luminant state of the light-emitting unit and comprises: a first control unit and a second control unit both having equivalent electronic elements. The first control unit and the second control unit have a signal generator and a signal synthesizer circuit. According to a signal fed back by the light-emitting unit and a dimming signal, the first signal generator outputs first working signals via the signal synthesizer circuit of the first control unit to determine the turn-on time of the switch. According to the first working signals and via the signal synthesizer circuit of the second control unit, the second signal generator outputs second working signals to the switch to determine the resonance frequency of the transformer.

Abstract: A signal sampler and method for high-speed input sampling of a signal are disclosed. A first sampler samples a data signal at a rising edge of a clock signal and generates a first sampled signal. A second sampler samples the data signal at a falling edge of an inverted clock signal and generates a second sampled signal. The first and second sampled signals may be combined to determine the next signal sampler output. An evaluation may include asserting the output signal if the first and second sampled signals are asserted, negating the output signal if the first and second sampled signals are negated, and toggling the output signal if the first and second sampled signals are in opposite logic states. The signal sampler and method of signal sampling may be incorporated in a semiconductor device, which may be fabricated on a semiconductor wafer and included in an electronic system.

Abstract: A system and method for managing performance states of a processor. An enclosure comprises a first processing board with a processor and a second processing board with a processor. A service processor may also be coupled to the enclosure via an interconnect. The second processing board is configured to store a value indicative of a maximum processor performance state for a processor on the second board. In response to a detected request for a transition to a first processor performance state, the processor on the second board is configured to transition to the first processor performance state, if the first processor state is less than or equal to the maximum processor performance state; and transition to the maximum processor performance state, if the first processor state is greater than the maximum processor state. The second processor board may store the value in response to a an operating environment condition detected elsewhere within the enclosure.

Abstract: A system and process enable a device to adjust the duration of various power modes based on usage of the device. The process includes operating a device at a fully operational power level, counting a first wait time, modifying a first wait time modifier in response to detection of image generating device use prior to expiration of the first wait time, and reducing power consumption from the fully operational level to a low power level in response to expiration of the first wait time.

Abstract: A method for regulating system power using a power governor for DRAM in a multi-node computer system regulating memory power consumption of an entire computer system employs a closed ring that connects all the power governors within the system to enable them to work in concert so that each of the power governors has the knowledge of memory activities within the entire system. They then control and limit the memory usage based on a true overall measurement instead of just local measurement. Each nodal power governor has memory command counter, ring number receiver, ring number transmitter, governor activation controller, and memory traffic controller. Each nodal power governor counts the weight of memory command. The degree of limiting actual memory activities can be programmed when the governor is active. Besides, the command priorities can be adjusted in activation too. A hybrid ring structure can be employed with a nodal power structure to achieve the fastest number circulation speed economically.

Abstract: Disclosed herein is a method for updating at least one of firmware, software, device components, and device configuration in an electronic device. The method and apparatus may employ at least one update agent or a plurality of update agents. An electronic device supporting multiple update agents may be adapted to prompt and facilitate an end-user to select at least one of the update agents to process update information contained in at least one update. The electronic device may also be adapted to prompt and facilitate an end-user to apply a particular update agent to update at least one of firmware, software, device components, device configuration, device information, and device parameters. The electronic device may also be adapted to prompt and facilitate an end-user to select an appropriate update agent from a plurality of available update agents based upon some information, such as for example, the type of update that the update agent is adapted to perform.

Abstract: A system for conserving battery life in a battery operated device such as a tire tag where there are several modes of operation. The typical mode is the deep sleep mode where the tag is generally inactive (no clock is running; however, an RC watchdog timer is running, which uses very little power). The tag spends most of its time in this low power mode. The tag periodically partially awakens to a lucid sleep mode (when the watchdog timer times out), initiates a low-speed clock, determines if it is time to enter a search mode by examining a search mode counter and, if it is not time, adjusts the search mode counter (e.g., decrements the counter by one), and returns to the deep sleep mode. The tag sleeps in the deep sleep mode most of its life in an effort to conserve battery power. During the deep sleep mode, because the clock oscillators are OFF, a deep sleep counter is adjusted (incremented or decremented) periodically (e.g., about every 18 ms) by an internal R/C oscillator.

Abstract: A system and method in which the receiving chip separately latches each half of the data received from the double data rate bus. Each half is launched as soon as it is available; one on the normal chip cycle time and the other is launched from a Master (L1) latch a half cycle into the normal chip cycle time. The first launched half of the data proceeds through the chip along its standard design chip path to be captured by the chips driving interface latch and launched again after one cycle of latency on the chip. The second half of the data proceeds through the chip one half cycle behind the first half, and is latched a half clock cycle later part way through the path into a Slave (L2) latch. On the next edge of the local clock, the data then continues from the L2 latch to the driving double data rate interface. This allows a half cycle set up time for the second half of the data so that it can be launched again, maintaining a one-cycle time on the chip.

Abstract: A double data rate launch system and method in which the two-to-one multiplexer select signal delay is programmable and can be adjusted individually for each system. This allows the amount of delay to be minimized based on the actual set up time required, not the worst-case set-up time. The select signal to the multiplexer is delayed sufficiently to compensate for non-uniformity of duty cycle of data at the inputs to the multiplexer. Compensation of the non-uniformity allows the data on the wire to have a uniform duty cycle for all data transferred regardless of which latch is sourcing the data. The multiplexer that selects data from the two latches which are launching data on the edge of different clocks has a select line that is delayed by a variable amount to tune the select such that the data is clean at the input to the multiplexer on all ports.

Abstract: An intermittent computing system state and intermittent computing module is described for a power-constrained personal computer. In the intermittent computing system state, the power-constrained personal computer may transition between sub-states of the intermittent computing system state according to an intermittent computing schedule. Each intermittent computing sub-state may be associated with hardware power sets and software power sets. Altering power supply to hardware components referenced by hardware power sets may alter power consumed in associated intermittent computing sub-states. A caching mechanism may be configured to make it likely that software components referenced by software power sets are loaded into powered storage types during associated intermittent computing sub-states. In the intermittent computing system state, periods of high functionality may be available over extended periods without the high power consumption associated with a continuous working system state.

Abstract: A CPU (1) automatically preserves the CPU context in a computer memory (5) that remains powered-up when the CPU is powered down in sleep mode. By means of the preserved CPU context, the CPU is able to instantly and transparently resume program execution at the instruction of the program that was asserted for execution when the CPU was powered down. The CPU is permitted to power down frequently, even during execution of a program, and results in reduced average overall power consumption.

Abstract: A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro using multiple clock gating inputs. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to be created for macros that contain multiple clock gating inputs. Energy tables are created based upon the macro's input switching factor and the clock activation percentage. The clock activation percentage is produced by turning on and off the multiple clock gating inputs during the simulations. These energy tables are generated from a minimum number of power simulations. By using clock activation percentage as a parameter accurate power estimations are produced.

Abstract: Provided are an apparatus and method of transmitting working context, which can minimize power consumption in a power-off standby mode of a portable apparatus including a system on a chip, where the method includes selecting a power-off standby mode, transmitting working context with respect to a hardware module, which is mounted on a semiconductor chip, to a predetermined memory, and storing the working context in the predetermined memory, transmitting the working context stored in the memory to a non-volatile memory outside the semiconductor chip, and storing the working context in the non-volatile memory, and executing the power-off standby mode; where the method may further include releasing the power-off standby mode, restoring the working context with respect to the hardware module, which is stored in the non-volatile memory, to the predetermined memory, and recovering the at least one hardware module to a state existing immediately before the power-off standby mode was executed by using the working con

Abstract: System and methods of synchronizing reference frequencies are disclosed. In an exemplary implementation, a method may comprise providing separate reference frequencies for each of a plurality of operational components. The method may also comprise connecting the separate reference frequencies to one another in a modular, fault-tolerant circuit topology. The method may also comprise synchronizing the separate reference frequencies so that each of the operational components operate at the same frequency.