Abstract: The present invention provides a method for automatic identification of the clock frequency of a system clock (15) for the configuration of a peripheral device (12), having the following steps: generation of a secondary clock (16) at a predetermined clock frequency; application of the system clock (15) and of the secondary clock (16) to a host (10); application of the system clock (15) and of the secondary clock (16) to the peripheral device (12); determination of the clock frequency of the system clock (15) in the peripheral device (12) by means of the secondary clock (16); and configuration of the peripheral device (12) using the determined system clock (15).

Abstract: A method of regulating power for multi-node computer system components has a closed-ring path that links all the power governors and circulating in the ring is a system power number that represents the power consumption of the entire system. Meanwhile, all the governors keep counting its local power consumption. Each time the number passes a governor, the governor will add its local count onto this number, store this number for future usage, and reset its local count. When the new number returns back to the same power governor, the governor will subtract the new number with its stored number to calculate the overall system power usage within a number circulation period. The system power number overflow problem is also detected with a counter if the incoming number is smaller then the number previously stored. The counter whose counting capacity is greater than the maximum system power usage on all the nodes within a number circulation period.

Abstract: According to one embodiment a CPU is disclosed. The CPU includes two or more clusters and a dispatch unit coupled to the two or more clusters. The dispatch unit steers instructions to the two or more clusters based upon the temperature of each of the clusters.

Abstract: A computer system which includes a CPU for performing various processes by program control and storage elements which store at least one operating system and a BIOS, wherein upon starting a system, the CPU recognizes the system's own hardware configuration, and starts a selected one operating system stored in the storage elements in accordance with the recognized hardware configuration under the control of the BIOS.

Abstract: An electronic device includes a system part having a plurality of electronic components; a system power supply outputting a system operating power by transforming electrical power supplied from the battery pack into the system operating power to operate the system part; a power selector outputting a system power selecting signal to turn the system part on/off according to an operation of a user; a micro control unit (MCU) controlling whether the system operating power of the system power supply is output; and an MCU power controller determining whether a control power to turn the MCU on is supplied by transforming electrical power supplied from the battery pack into the control power, based on the system power selecting signal transmitted from the power selector and controlling the MCU to be turned on/off.

Abstract: An electronic processing system contains a power supply subsystem and a multi-processor module. Programmable control circuitry manages power consumption in the electronic system by allocating priority among a plurality of competing demands, such as total power consumption, power consumption at any one of the processors, and thermal measurements. Analog sense measurements of incoming power are transmitted to the control circuits, which are protected from noise through use of an isolation barrier established by a linear isolation amplifier.

Abstract: A method for dynamically adjusting central processing unit (CPU) frequency. Firstly, a translation table is provided between multi-layer of CPU usage percentage and front-side bus operation frequency. Secondly, a current usage percentage of the CPU is obtained. Lastly, the operation frequency of the front-side bus is adjusted to a corresponding layer according to the current usage rage, so that the current usage rage is located within the range of CPU usage percentage that is defined by corresponding layer.

Abstract: Provided are an apparatus and method of transmitting working context, which can minimize power consumption in a power-off standby mode of a portable apparatus including a system on a chip, where the method includes selecting a power-off standby mode, transmitting working context with respect to a hardware module, which is mounted on a semiconductor chip, to a predetermined memory, and storing the working context in the predetermined memory, transmitting the working context stored in the memory to a non-volatile memory outside the semiconductor chip, and storing the working context in the non-volatile memory, and executing the power-off standby mode; where the method may further include releasing the power-off standby mode, restoring the working context with respect to the hardware module, which is stored in the non-volatile memory, to the predetermined memory, and recovering the at least one hardware module to a state existing immediately before the power-off standby mode was executed by using the working con

Abstract: Several processors have specifications setting forth that each processor be coupled to a separate specified voltage regulator circuit. Instead, a number of specified voltage regulator circuit(s) is coupled to the several processors. The number of voltage regulator circuit(s) is less than the number of processors. The processors and voltage regulator circuit(s) are coupled to a module, and a thermal limit for the module is maintained because the several processors are coupled to the smaller number of voltage regulator circuits.

Abstract: An integrated circuit (IC) chip (100) containing a plurality of voltage islands (124I-M) containing corresponding functional blocks (104I-M) that can be selectively fenced, i.e., powered down, while saving the states of the corresponding inputs, and unfenced in order to manage power consumption of the chip. Each fencable functional block includes a power switch (140I-M) and state-saving circuitry (148I-M) for saving the state of the inputs to that functional block. A power modulation unit (PMU) (132) generates fencing signals (144I-M) that control the power switches and state-saving circuitries so as to selectively fence the corresponding functional blocks. The PMU generates the fencing signals as a function of one or more operating arguments.

Abstract: In a recording/reproducing apparatus capable of communicating with a data transmission site and the other apparatus through a network, a control unit controls the recording and reproducing of the information based on firmware. A receiving unit receives first information from the other apparatus through the network, the first information including a request of updating of the firmware. An output unit outputs second information to the data transmission site through the network in response to reception of the first information, the second information including a request of transmitting third information used for updating the firmware. A unit acquires the third information from data transmission site through the network to update the firmware.

Abstract: A free-running secure clock in a computing device that is adjustable by a user of the device so long as cumulative adjustments do not exceed a predicted clock drift. The clock may be initially set by the user or by a trusted time authority or the like. Such a clock may be required in a trust-based system that measures a temporal requirement against the clock.

Abstract: A processor with an adjustable operating frequency and method thereof. The pipeline processor includes a clock providing module for providing a reference clock, and a processing core coupled to the clock providing module for processing a first instruction according to the reference clock. The clock providing module contains a multi-phase clock generator for generating a plurality of original clocks with different phases, and a phase selector for selecting an original clock to generate the reference clock according to the first instruction.

Abstract: A computer system has multiple performance states. The computer system periodically determines utilization information for the computer system and adjusts the performance state according to the utilization information. If a performance increase is required, the computer system always goes to the maximum performance state. If a performance decrease is required, the computer system steps the performance state down to a next lower performance state.

Abstract: The present invention provides a data processing apparatus and method of controlling access to a shared resource. The data processing apparatus has a plurality of processors operable to perform respective data processing operations requiring access to the shared resource, and a path is provided interconnecting the plurality of processors. An access control mechanism is operable to control access to the shared resource by the plurality of processors, each processor being operable to enter a power saving mode if access to the shared resource is required but the access control mechanism is preventing access to the shared resource by that processor. Further, each processor is operable, when that processor has access to the shared resource, to issue a notification on the path when access to the shared resource is no longer required by that processor. A processor in the power saving mode is arranged, upon receipt of that notification, to exit the power saving mode and to seek access to the shared resource.

Abstract: An information handling system includes support for dynamic power throttling. In one embodiment, an information handling system includes power level detection and power control modules. The power level detection module may monitor power consumption for the information handling system and may automatically transmit power level data to a power level manager, based on the monitored power consumption. The power control module may receive power control data from the power level manager. The power control module may also automatically adjust power consumption of the information handling system, in accordance with the power control data received from the power level manager. In another embodiment, an information handling system may include an interface and a power level manager. The power level manager may receive power information for computers via the interface, may automatically compute an adjusted power threshold setting, and may automatically transmit the adjusted power threshold setting to a computer.

Abstract: A novel personal electronic device includes a processor having first (embedded) and second (non-embedded) cores including associated operating systems and functions. In one aspect, the first core performs relatively limited functions, while the second core performs relatively broader functions under control of the first core. Often the second core requires more power than the first core and is selectively operated by the first core to minimize overall power consumption. Protocols for functions to be performed by the second core may be provided directly to the second core and processed by the second core. In another aspect, a display controller is designed to interface with both cores. In another aspect, the operating systems work with one another. In another aspect, the first core employs a thermal control program. Advantages of the invention include a broad array of functions performed by a relatively small personal electronics device.

Abstract: A method, an apparatus and a carrier medium storing instructions to implement the method. The method is in a first wireless station of a wireless network, and includes wirelessly receiving a signal corresponding to a packet wirelessly transmitted by a second wireless station. The packet includes a subpacket and a check sequence. The method further includes verifying the integrity of the subpacket, the verifying at least using the check sequence. The method further includes, in the case that the subpacket fails the verifying, reducing the power consumption of at least one component in the first wireless station for a time interval.

Abstract: An object of the present invention is to provide a display unit and a power save controller capable of reducing the power consumption in a power save mode.

Abstract: An integrated circuit has a power grid and a set of independently switchable voltage islands, together with a system and method for measuring the voltage and history of the voltage on the power grid to determine the correct time to allow a large capacitive load (such as a voltage island) to be switched on to or off the power grid.