Abstract: It is aimed at providing a data processor capable of suppressing a sudden current change from the viewpoint of a synchronization clock. A data processor 1 comprises a clock pulse generation circuit and a circuit module operating on input clock signal CLKi output from the clock pulse generation circuit. In case of restoration from a power-on reset period or a standby state, the clock pulse generation circuit stepwise changes frequencies of the clock signal from low to high frequencies. This makes it possible to prevent a power supply current from suddenly increasing in case of restoration from the power-on reset period or the standby state.

Abstract: Dynamic hardware partitioning of symmetric multiprocessing systems enables on-the-fly provisioning of servers of varying performance characteristics by configuring physical partitions having selectable numbers of processors. Processors are directed to disable included coherency links (for example by de-asserting respective Power-Good indicators to each of the processors). Then processors selected for inclusion in a first physical partition are directed to form coherency links with all adjacent processors (for example by asserting the respective Power-Good indicators to each of the processors of the first physical partition). All other processors in the system remain isolated (i.e. their respective Power-Good indicators remain de-asserted). The processors of the first physical partition are then directed to fetch and execute instructions (for example by de-asserting respective Reset indicators to each of the processors).

Abstract: Information usable in determining the quality of time produced by a clock of a processing environment is obtained. The information is obtained directly by an application program absent use of a supervisor service, such as an operating system or operating system service. The application program invokes an instruction that returns a parameter block that includes the information.

Abstract: Programmable logic circuits are changeable circuit components based on circuit data. A circuit data memory stores a plurality of circuit data and performance requirements. A feature data memory stores feature data of each programmable logic circuit. A control unit calculates a minimum voltage of the plurality of programmable logic circuits to execute the plurality of circuit data based on the performance requirements, and selectively assigns the plurality of circuit data to the plurality of programmable logic circuits so that the performance requirement of circuit data assigned to each programmable logic circuit is within the operation range of the programmable logic circuit at the minimum voltage. A supply unit supplies the minimum voltage to the plurality of programmable logic circuits.

Abstract: An information processing apparatus is connectable to a bus that is connected to a further apparatus. A detecting circuit detects whether the bus is connected to the information processing apparatus. When the detecting circuit detects that the bus is connected to the information processing apparatus, a control circuit controls a power supply circuit such that the power supply circuit provides power to a further circuit. When the detecting circuit detects that the bus is not connected to the information processing apparatus, the control circuit controls the power supply circuit such that the power supply circuit does not provide the power to the further circuit.

Abstract: A power-managed server and method for managing power consumption is disclosed. According to one embodiment, a power-managed server data processing system is provided among a plurality of server data processing systems which comprises a power management communication port to communicatively couple the power-managed server data processing system to a power management server data processing system of the plurality of server data processing systems. The power-managed server data processing system of the described embodiment further comprises a system management processor coupled to the power management communication port which comprises power-managed logic configured to transmit power management data to the power management server data processing system and to receive a power management command utilizing the power management communication port. Moreover, the power management command is generated utilizing the power management data, and the power management data comprises power management capability data.

Abstract: One embodiment of the present invention provides a system that facilitates phase-buffering on a bit-by-bit basis using a control queue. The system includes a control queue, wherein a stage in the control queue is configured to accept both a first control signal and a second control signal, wherein the first control signal and the second control signal are mutually exclusive, wherein the first control signal being asserted indicates the value of a corresponding bit is zero, while the second control signal being asserted indicates the value of the corresponding bit is one. A forward-transfer mechanism couples the first control signal or the second control signal from the input of the stage through storage elements to the output of the stage. A reverse transfer mechanism accepts an acknowledgement signal at the output of the stage and transfers the acknowledgement signal through a storage element to the input of the stage.

Abstract: A standby power control apparatus is developed for monitoring the peripheral devices connected to a computer and the current computer status. A power-supply voltage applied to the peripheral devices and the computer can be completely blocked depending on the result of the monitoring. The standby power control apparatus is comprised of: a power-supply unit, interface unit, I/O terminal unit for transmitting the input signals received from a mouse or keyboard to the microprocessor, a switching unit, an individual load detector for detecting the load of a peripheral device, a sensor for determining the user status, a microprocessor for actuating the switching unit according to first to third input signals to control the voltage generated from the sockets, an individual drive signal generator for generating a drive signal to switch the switching unit; and a monitoring/management unit for transmitting a power-supply control command signal to the microprocessor, and providing the various administrator setup menus.

Abstract: The objective is to reduce the downtime of a printing system in the printing industry. Provision is therefore made to supply the drive regulators (3) of a printing system (1) simultaneously with a plurality of clock signals. Each of the drive regulators (3) independently selects one of the clock signals for synchronization. In the event of failure of a signal source, the printing system is not interrupted but the drive regulators (3) switch automatically to the clock still present.

Abstract: A method and apparatus for updating the system configuration settings of a computer system Embodiments include a remote system configuration system that enables a user to update the system configuration of a target machine from a server machine over a network or similar communications system. Another embodiment includes a system configuration method using a bus master device to write system configuration data into a target computer system.

Abstract: An inline power controller includes at least one analog interface circuit module (AICM) having a first analog input node for receiving an inline power port voltage, a second analog input node for receiving an inline power port current, a first analog output for effecting an inline power port voltage, a second analog output for effecting an inline power port current, and a digital interface converting the received inline power port voltage to a digital value, the inline power port current to a digital value, a first digital value to the first analog output and a second digital value to the second analog output. A digital serial bus (DSB) couples the AICM to a digital controller via digital serial bus interfaces (DSBIs).

Abstract: A method and apparatus for managing power sequencing in a data storage system. The turn-on or spin-up sequence for the media drives in an array of media drives is selectively controlled such that the overall rush current is reduced. The individual drive components are characterized to determine a power profile for each such component. A closed-loop process is then used to manage and reduce peak power requirements when starting up or spinning up an array of media drives using the drive profiles. The media drives can also be organized as a plurality of sets of drives, and a power profile for each set of drives is used to manage and reduce peak power requirements.

Abstract: Provided are a method, system, deployment and article of manufacture, wherein in one embodiment, a mode of operation may be switched to a service mode by detecting a device inserted into a connector of an input/output port of a system. In the illustrated embodiment, the device has a connector and a wire which loops a code received from the input/output port back to the input/output port. Upon detecting receipt of the transmitted code, the mode of operation may be switched to a service mode. Other embodiments are described and claimed.

Abstract: According to some embodiments, an Ethernet link speed is determined based on a power-related configuration, and an Ethernet link is negotiated at the link speed. Embodiments may also include determination of whether a power-conserving protocol is enabled, and/or may be implemented by an Ethernet controller.

Abstract: Input/output (I/O) devices may be controlled to reduce power consumption of a computer system. A power consumption metric for the I/O devices connected to the computer system is determined. At least one of the I/O devices is selected based on the determined power consumption metric, and power consumption for the selected I/O device is reduced.

Abstract: Apparatus and a method for booting each of a plurality of computer processor nodes in a cluster system to run the same cluster operating system.

Abstract: Synchronization is attained between a source clock domain and a target clock domain of arbitrary frequency ratios and each of which periodically has edges nominally aligned to edges of a reference clock signal, marked by the assertion of a periodic sync signal. The periodic sync signal, synchronous with the source clock, is used to output to an unload pointer counter in the target clock domain the deassertion of a reset signal prior to the nominal alignment of the source clock and the target clock for sampling on the nominally aligned target clock edge. The deassertion of the reset signal is output to a load pointer in the source clock domain coincident with the nominally-aligned edges of the source clock and the target clock. Both loading and unloading start based on the reset deassertion being sampled on the nominally aligned edges in the appropriate clock domain.

Abstract: A system, method and computer program product for steering a time-of-day (TOD) clock for a computer system having a physical clock providing a time base for executing operations that is stepped to a common oscillator. The method includes computing a TOD-clock offset value (d) to be added to a physical-clock value (Tr) value to obtain a logical TOD-clock value (Tb), where the logical TOD-clock value is adjustable without adjusting a stepping rate of the oscillator.

Abstract: A method, a computer program, and an apparatus are provided for generating circuit energy models for a macro using multiple clock gating inputs. Circuit energy models are used to estimate system power consumption. The present invention enables circuit energy models to be created for macros that contain multiple clock gating inputs. Energy tables are created based upon the macro's input switching factor and the clock activation percentage. The clock activation percentage is produced by turning on and off the multiple clock gating inputs during the simulations. These energy tables are generated from a minimum number of power simulations. By using clock activation percentage as a parameter accurate power estimations are produced.

Abstract: A power governor for DRAM in a multi-node computer system regulating memory power consumption of an entire computer system employs a closed ring that connects all the power governors within the system to enable them to work in concert so that each of the power governors has the knowledge of memory activities within the entire system. They then control and limit the memory usage based on a true overall measurement instead of just local measurement. Each nodal power governor has memory command counter, ring number receiver, ring number transmitter, governor activation controller, and memory traffic controller. Each nodal power governor counts the weight of memory command. The degree of limiting actual memory activities can be programmed when the governor is active. Besides, the command priorities can be adjusted in activation too. A hybrid ring structure can be employed with a nodal power structure to achieve the fastest number circulation speed economically.