Patents Examined by Martin Sulsky
  • Patent number: 6242292
    Abstract: In producing a semiconductor device by annealing with laser light irradiation, while a linear laser light is scanned in a direction perpendicular to a line, the annealing is performed for a semiconductor material. In this state, since an anneal effect in a beam lateral direction corresponding to a line direction is 2 times or more different than that in the scanning direction, a plurality of semiconductor elements are formed along a line direction in which the linear laser light is irradiated. Also, a line direction connecting the source and drain region of a thin film transistor is aligned to the line direction of the linear laser light.
    Type: Grant
    Filed: December 14, 1995
    Date of Patent: June 5, 2001
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Naoto Kusumoto, Koichiro Tanaka
  • Patent number: 6130161
    Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is converted to an intermetallic layer. A layer of copper intermetallics with halfnium, lanthanum, zirconium or tin, is provided to improve the electromigration resistance and to reduce defect sensitivity. A method is also provided to form a cap atop copper lines, to improve corrosion resistance, which fully covers the surface. Structure and methods are also described to improve the electromigration and corrosion resistance by incorporating carbon atoms in copper intersititial positions.
    Type: Grant
    Filed: May 30, 1997
    Date of Patent: October 10, 2000
    Assignee: International Business Machines Corporation
    Inventors: Leon Ashley, Hormazdyar M. Dalal, Du Binh Nguyen, Hazara S. Rathore, Richard G. Smith
  • Patent number: 6090689
    Abstract: A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200.degree. C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: July 18, 2000
    Assignee: International Business Machines Corporation
    Inventors: Devendra Kumar Sadana, Orin Wayne Holland
  • Patent number: 6090703
    Abstract: A interconnect structure is provided having a conductor with enhanced thickness. The conductor includes an upper portion and a lower portion, wherein the lower portion geometry is sufficient to increase the current-carrying capacity beyond that provided by the upper portion. The lower portion is formed by filling a trench within an upper dielectric region, and the upper portion is formed by selectively removing a conductive material from the upper dielectric surface except for regions directly above the lower portion. The upper and lower portions thereby form a conductor of enhanced cross-section which can be produced by modifying a via-etch mask, rather than having to reconfigure and/or move interconnect features formed by a metal mask.
    Type: Grant
    Filed: October 2, 1998
    Date of Patent: July 18, 2000
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Basab Bandyopadhyay, H. Jim Fulford, Jr., William S. Brennan, Fred N. Hause, Robert Dawson, Mark W. Michael
  • Patent number: 6087193
    Abstract: A non-power generating current limiting device such as a field effect transistor is provided to output a regulated current in dependence upon a control voltage. An electron field emitter is connected to a drain or output of the non-power generating current limiting device to receive the regulated current. A tip of the electron field emitter emits electrons towards a collector anode. An extractor gate can be provided between the electron field emitter and the collector anode to control the rate of electron emission from the electron field emitter. Because the non-power generating current limiting device regulates the current to the electron field emitter, a maximum current output of the electron field emitter is limited to the regulated current from the voltage controlled current source. The electron field emitter is thus protected from destruction due to excess current. The non-power generating current limiting device can also be used to modulate electron emission from the field emitter.
    Type: Grant
    Filed: May 12, 1994
    Date of Patent: July 11, 2000
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Henry F. Gray
  • Patent number: 6077759
    Abstract: A silicon oxide film is formed as an under film on a glass substrate and then an amorphous silicon film is formed thereon. Using hydrogen plasma produced by a frequency of 50 to 100 MHz, the amorphous silicon film formed on the glass substrate is processed. In this plasma processing, hydrogen atoms in the amorphous silicon film is combined with hydrogen atoms in the plasma with a high energy state, so that a gas is generated and the dehydrogenation from the amorphous silicon film progresses. After the dehydrogenation is completed, the heating treatment is performed to crystallize the amorphous silicon film and to transform the amorphous silicon film into a crystalline silicon film.
    Type: Grant
    Filed: September 12, 1997
    Date of Patent: June 20, 2000
    Assignee: Semiconductor Energy Laboratory Co.,
    Inventors: Shunpei Yamazaki, Satoshi Teramoto
  • Patent number: 6077729
    Abstract: A memory device having a plurality of memory arrays. Each array has a plurality of memory cells, each memory cell including an electrode defining a respective contact area. Each memory array is formed by depositing a continuous chalcogenide layer. This chalcogenide layer, even when continuous, will have active areas formed above the electrodes, and a conductive layer electrically coupling at least a portion of the active areas. The memory array can also include a dielectric volume surrounding at least a portion of the plurality of electrodes. The electrodes can be contacts, plugs or pillars deposited in etched openings in the dielectric volume.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: June 20, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Steven T. Harshfield
  • Patent number: 6071764
    Abstract: After a pattern is transferred on silicon film crystallized by annealing, the silicon film is annealed by radiation of intense rays for a short time. Especially, in the crystallizing process by annealing, an element which promotes crystallization such as nickel is doped therein. The area not crystallized by annealing is also crystallized by radiation of intense rays and a condensed silicon film is formed.After a metal element which promotes crystallization is doped, annealing by light for a short time is performed by radiating intense rays onto the silicon film crystallized by annealing in an atmosphere containing halide. After the surface of the silicon film is oxidized by heating or by radiating intense rays in a halogenated atmosphere and an oxide film is formed on the silicon film, the oxide film is then etched. As a result, nickel in the silicon film is removed.
    Type: Grant
    Filed: June 28, 1995
    Date of Patent: June 6, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Hideto Ohnuma, Yasuhiko Takemura
  • Patent number: 6071765
    Abstract: A method of forming a polycrystalline silicon thin film improved in crystallinity and a channel of a transistor superior in electrical characteristics by the use of such a polycrystalline silicon thin film. An amorphous silicon layer of a thickness preferably of 30 nm to 50 nm is formed on a substrate. Next, substrate heating is performed to set the amorphous silicon layer to preferably 350.degree. C. to 500.degree. C., more preferably 350.degree. C. to 450.degree. C. Then, at least the amorphous silicon layer is irradiated with laser light of an excimer laser energy density of 100 mJ/cm.sup.2 to 500 mJ/cm.sup.2, preferably 280 mJ/cm.sup.2 to 330 mJ/cm.sup.2, and a pulse width of 80 ns to 200 ns, preferably 140 ns to 200 ns, so as to directly anneal the amorphous silicon layer and form a polycrystalline silicon thin film. The total energy of the laser used for the irradiation of excimer laser light is at least 5 J, preferably at least 10 J.
    Type: Grant
    Filed: August 20, 1997
    Date of Patent: June 6, 2000
    Assignee: Sony Corporation
    Inventors: Takashi Noguchi, Tohru Ogawa, Yuji Ikeda
  • Patent number: 6057235
    Abstract: A process of forming a layer of conductive material over a layer of insulating material is provided. A wafer is positioned on a wafer platform such that it is thermally and electrically coupled to the wafer platform. A clamping ring engages the peripheral edge of the wafer such that the wafer is held against the top surface of the wafer platform. The clamping ring is electrically coupled to the wafer pedestal. The wafer is exposed to a plasma comprising conductive material and an initial layer of conductive material is formed over the insulating layer until the top surface of the wafer is electrically coupled to the clamping ring. The wafer pedestal is then electrically biased and additional conductive material is formed. Once the initial layer of conductive material is electrically coupled to the clamping ring, the potential difference between the top and bottom surface of the wafer is zero such that arcing through the wafer is reduced.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: May 2, 2000
    Assignee: Micron Technology, Inc.
    Inventors: Shane P. Leiphart, Randle D. Burton
  • Patent number: 6057236
    Abstract: Improved methods for forming metal-filled structures in openings on substrates for integrated circuit devices are obtained by the formation of a discontinuous metal liner by CVD in an opening to be filled. The discontinuous metal liner surprisingly provides wetting equivalent to or better than continuous layer CVD liners. The CVD step is followed by depositing a further amount of metal by physical vapor deposition over the discontinuous layer in the opening, and reflowing the further amount of metal to obtain the metal-filled structure.The interior surface of the opening is preferably a conductive material such as titanium nitride. Preferably, the discontinuous metal layer is made of aluminum. The metal deposited by PVD is preferably aluminum or an aluminum alloy. The methods of the invention are especially useful for the filling of contact holes, damascene trenches and dual damascene trenches. The methods of the invention are especially useful for filling structures having an opening width less than 250 nm.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: May 2, 2000
    Assignee: International Business Machines Corporation
    Inventors: Larry Clevenger, Mark Hoinkis, Roy C. Iggulden, Stefan J. Weber
  • Patent number: 6048803
    Abstract: A semiconductor device having relatively low permittivity fluorine bearing oxide between conductive lines and a method for fabricating such a device is provided. At least two adjacent conductive lines are formed over a substrate. An oxide layer is formed between the adjacent conductive lines. A mask is formed over the oxide layer and selectively removed to expose a portion of the oxide layer between the adjacent conductive lines. A fluorine bearing species is implanted into the exposed portion of the oxide layer to reduce the permittivity of the oxide layer between the adjacent conductive lines. The permittivity or dielectric constant of the oxide layer between the adjacent conductive lines can, for example, be reduced from about 3.9 to 4.2 to about 3.0 to 3.5.
    Type: Grant
    Filed: August 19, 1997
    Date of Patent: April 11, 2000
    Assignee: Advanced MicroDevices, Inc.
    Inventors: Mark I. Gardner, Daniel Kadosh
  • Patent number: 6040224
    Abstract: A microscopic interconnection pattern and a gate electrode can be prevented from being deformed when a first region requiring high temperature heating, such as a source-drain region and a second region which should be prevented from being heated at high temperature, such as a microscopic interconnection pattern and a gate electrode are formed on the same semiconductor substrate. A first region which requires high temperature heating and a second region which should be avoided from being heated at high temperature are formed on a semiconductor substrate. In that case, the second region is composed of a narrow portion (1) and wide portions (2) wider than the narrow portion (1) formed on respective ends of the narrow portion 1. Then, the semiconductor substrate is photo-annealed.
    Type: Grant
    Filed: April 30, 1997
    Date of Patent: March 21, 2000
    Assignee: Sony Corporation
    Inventor: Hironori Tsukamoto
  • Patent number: 6040249
    Abstract: A method of providing a MOSFET having improved gate oxide diffusion barrier properties, which comprises providing a partially fabricated MOSFET having an exposed gate oxide surface. During MOSFET fabrication, the surface of the exposed gate oxide is converted to an oxynitride by applying one or both of ions or free radicals of nitrogen to the exposed gate oxide surface. Fabrication of the MOSFET is then completed in standard manner.
    Type: Grant
    Filed: August 8, 1997
    Date of Patent: March 21, 2000
    Assignee: Texas Instruments Incorporated
    Inventor: Thomas C. Holloway
  • Patent number: 6037273
    Abstract: A method of forming an oxide on a substrate. According to the method of the present invention a substrate is placed in a chamber. An oxygen containing gas and a hydrogen containing gas are then fed into the chamber. The oxygen containing gas and the hydrogen containing gas are then caused to react with one another to form water vapor in the chamber. The water vapor then oxidizes the substrate.
    Type: Grant
    Filed: March 2, 1998
    Date of Patent: March 14, 2000
    Assignee: Applied Materials, Inc.
    Inventors: Christian M. Gronet, Peter A. Knoot, Gary E. Miner, Guangcai Xing, David R. Lopes, Satheesh Kuppurao
  • Patent number: 6030900
    Abstract: In a method for the production of a spacer layer in a structure in a first step a structure is produced by anisotropic dry etching, and in a further step an oxide layer is deposited with an organic silicon precursor at a pressure of p=0.2-1 bar and a temperature of 200.degree. C. to 400.degree. C.
    Type: Grant
    Filed: February 4, 1998
    Date of Patent: February 29, 2000
    Assignee: Siemens Aktiengesellschaft
    Inventors: Thomas Grassl, Manfred Engelhardt
  • Patent number: 6027950
    Abstract: A method for preventing oxygen microloading of an SOG layer. In one embodiment of the present invention, hydrogen is introduced into an etching environment. An etching step is then performed within the etching environment. During the etching step an SOG layer overlying a TEOS layer is etched until at least a portion of the underlying TEOS layer is exposed. The etching step continues and etches at least some of the exposed portion of the TEOS layer. During etching, the etched TEOS layer releases oxygen. The hydrogen present in the etching environment scavenges the released oxygen. As a result, the released oxygen does not microload the SOG layer. Thus, the etchback rate of the SOG layer is not significantly affected by the released oxygen, thereby allowing for controlled etchback of the SOG layer.
    Type: Grant
    Filed: August 5, 1997
    Date of Patent: February 22, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Ian Robert Harvey, Calvin Todd Gabriel
  • Patent number: 6027960
    Abstract: A laser-annealing method includes the steps of a first step of cleaning a non-monocrystal silicon film formed on a substrate, and a second step of laser-annealing the non-monocrystal silicon film in an atmosphere containing oxygen therein, wherein the first and second steps are conducted continuously without being exposed to the air. Also, a laser-annealing device includes a cleaning chamber, and a laser irradiation chamber, wherein a substrate to be processed is transported between the cleaning chamber and the laser irradiation chamber without being exposed to the air.
    Type: Grant
    Filed: October 23, 1996
    Date of Patent: February 22, 2000
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Naoto Kusumoto, Toru Takayama, Masato Yonezawa
  • Patent number: 6028012
    Abstract: A method of fabricating a semiconductor structure involving the steps of providing a SiC substrate, treating the SiC substrate with an N.sub.2 O-containing plasma, and forming a dielectric layer on the surface of the pretreated SiC substrate. A semiconductor structure produced by the method above. An apparatus for forming a dielectric layer on a SiC substrate including a deposition chamber in which the SiC substrate is placed, a first valve that connects a first source providing N.sub.2 O to the deposition chamber, a second valve that connects a second source providing reactants that form the dielectric layer to the deposition chamber, an energy source for producing an N.sub.2 O-containing plasma from N.sub.2 O released from the first source by the first valve, and a controller that programs providing power to the energy source and opening and closing the first and second valves into two phases.
    Type: Grant
    Filed: December 4, 1996
    Date of Patent: February 22, 2000
    Assignee: Yale University
    Inventor: Xiewen Wang
  • Patent number: 6025217
    Abstract: Method of forming a uniform polycrystalline semiconductor thin film by laser annealing. The method is started with preparing a substrate having an insulating layer which has a relatively low thermal conductivity and a thickness of more than 20 nm. Then, an amorphous silicon thin film having a relatively high thermal conductivity is formed to a thickness of less than 35 nm on the insulating layer. Thereafter, the amorphous silicon thin film is irradiated with laser beam to impart thermal energy to the film. In this way, the amorphous film is converted into a polysilicon thin film. Since the thickness of the amorphous silicon film is less than 35 nm, polysilicons having uniform grain diameters can be grown.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: February 15, 2000
    Assignee: Sony Corporation
    Inventors: Yasuhiro Kanaya, Masaru Yamazaki, Masahiro Fujino, Nobuaki Suzuki, Midori Kuki