Abstract: A thin film transistor for a liquid crystal display includes a substrate; an active layer having source and drain regions over the substrate; a first insulating layer adjacent to the active layer and having first and second surfaces, the first surface being on an opposite side to the second surface, and the active layer being adjacent to the second surface of the first insulating layer; a gate electrode adjacent to the first surface of the first insulating layer; a first electrode in contact with the source region; a second electrode in contact with the drain region; a second insulating layer on the second electrode; and a third insulating layer over a resultant structure of the substrate.

Abstract: There are disclosed a method and apparatus for manufacturing semiconductor devices. The surface of each semiconductor substrate is exposed to cyanide ions (CN.sup.-) in order to reduce the density of interface states at the insulating film/semiconductor interface. For this purpose, the semiconductor substrate is immersed into a cyan compound solution or is exposed to a cyan compound gas, so that cyanide ions (CN.sup.-) are bonded to dangling bonds at the surface of the semiconductor substrates. As a result, the interface states at the insulating film/semiconductor interface can be reduced.

Abstract: An electronic device comprises a semiconductor substrate (2) having a cavity (32) extending into the substrate (2), a membrane (8) formed over the semiconductor substrate so as to extend across the cavity (32) in the semiconductor substrate and an active region (14, 30) supported by the membrane (8) and positioned adjacent the cavity (32). The membrane (8) comprises a single dielectric layer formed of an oxy-nitride material.

Abstract: A silicon oxide insulator (SOI) device includes an SOI layer supported on a silicon substrate. A body region is disposed on the SOI layer, and the body region is characterized by a first conductivity type. Source and drain regions are juxtaposed with the body region, with the source and drain regions being characterized by a second conductivity type. A transition region is disposed near the body region above the SOI layer, and the conductivity type of the transition region is established to be the first conductivity type for suppressing floating body effects in the body region and the second conductivity type for isolating the body region. An ohmic connector contacts the transition region and is connected to a drain power supply when the source and drain are doped with N-type dopants. On the other hand, the power supply is a source power supply when the source and drain are doped with P-type dopants.

Abstract: A thin film transistor includes: a) a thin film transistor layer comprising a source region, a channel region and a drain region; the thin film transistor layer further comprising a drain offset region positioned between the drain region and the channel region; b) the channel region being substantially polycrystalline and having a first average crystalline grain size; and c) the drain offset region being substantially polycrystalline and having a second average crystalline grain size, the second average crystalline grain size being larger than the first average crystalline grain size. A method for forming such a construction using polycrystalline materials, preferably polysilicon, and an amorphizing silicon implant with subsequent recrystallization is also disclosed.

Abstract: Methods are disclosed that enhance the contrast between alignment targets and adjacent materials on a semiconductor wafer. According to a first embodiment, the TiN layer that is deposited during an earlier processing step is stripped away to enhance the reflectivity of the metal layer. According to a second embodiment, a reflective coating is added over the metal layer to enhance the reflectivity of the metal layer. According to a third embodiment, a reflective coating is added over the entire wafer to enhance the reflectivity of the metal layer. According to a fourth embodiment, an anti-reflective coating in a sandwich structure is added to reduce the reflectivity of the material adjacent the alignment targets. According to a fifth embodiment, an organic anti-reflective coating is added to reduce the reflectivity of the material adjacent the alignment targets.

Abstract: A vertical field effect transistor (1) and a method of manufacturing thereof are disclosed, in which a buried layer (3) of a conduction type opposite to that of a substrate (2) is formed to a predetermined depth in the substrate (2) by ion implantation. The bottom of recess (2a) for forming a protrusion (2b) on the substrate (2) is located within the corresponding one of the buried layer (3). The width of the recess (2a) is set smaller than the width of the buried layer (3). The surface of the protrusion (2b) and the bottom of the recess (2a) are formed with impurities regions (4a, 4b; 5a, 5b) constituting a source and a drain, respectively. A channel length (L) of the channel region formed on the side wall of the protrusion (2b) is defined by the distance between the buried layer (3) and the impurities regions (5a, 5b) on the surface of the protrusion (2b).

Abstract: An improved process is provided for amorphizing portions of a silicon substrate and a polysilicon gate electrode surface to be converted to metal silicide by subsequent reaction of the amorphized silicon with a metal layer applied over the silicon substrate and polysilicon gate electrode after the amorphizing step. The improvement comprises implanting the exposed surface of the silicon substrate and the surface of the polysilicon gate electrode with a beam of amorphizing ions at an angle of at least 15.degree. to a line perpendicular to the plane of the surface of the silicon substrate to thereby inhibit channeling of the implanted ions through the gate electrode to the underlying gate oxide and channel of the MOS structure. The implant angle of the beam of amorphizing ions is preferably at least 30.degree., but should not exceed 60.degree., with respect to a line perpendicular to the plane of the surface of the silicon substrate.

Abstract: A method for producing integrated circuit devices comprises the steps of forming and packaging such devices at the wafer scale, including forming a plurality of chip circuits with bond pads, adhesively fixing a plate of glass to the active surface of the wafer, slicing the wafer, applying a sealant layer to the backside of the wafer, forming contact holes through the upper glass plate, metallizing the glass plate and singulating the individual chips. Use of etchable glass for the package and palladium for metallization provides an advantageous construction method.

Abstract: It is intended to provide a technique of separately forming thin-film transistors disposed in a peripheral circuit area and those disposed in a pixel area in accordance with characteristics required therefor in a manufacturing process of semiconductor devices to constitute a liquid crystal display device. In an annealing step by laser light illumination, laser light is selectively applied to a semiconductor thin-film by partially masking it. For example, to illuminate the peripheral circuit area and the pixel area with laser light under different conditions in manufacture of an active matrix liquid crystal display device, laser light is applied at necessary illumination energy densities by using a mask. In this manner, a crystalline silicon film having a necessary degree of crystallinity in a selective manner can be obtained.

Abstract: A metal organic chemical vapor deposition apparatus comprising a source ampule, a liquid micro-pump, a vaporizer equipped with a solvent supply means, and a reactor. A reactant dissolved in a solvent in the source ampule is transferred to the vaporizer by the liquid micro-pump. A sufficient amount of the solvent is additionally fed to the vaporizer by the solvent supply means, concurrently with the transfer, and vaporized along with the reactants. After being vaporized in the vaporizer, the reactant is injected to the reactor by carrier gas and deposited on a semiconductor substrate to form a high dielectric thin film. By virtue of the additional supplied solvent, the recondensation of the reactant in the vaporizer, which is attributed to the separation of the solvent from the reactant, can be prevented in the vaporizer and in the transfer line between the vaporizer and the reactor.

Abstract: A method of forming a dual damascene structure includes forming an oxide layer and a mask layer there on, which both have protuberances over the conductive layers. Then a chemical mechanical polishing is performed to remove the protuberances and to form openings. The protuberances are above the conductive layers.

Abstract: The present invention proves a method and apparatus for manufacturing a polysilicon TFT without a defective activated area in a channel region below a gate. According to the instant invention, a dopant is implanted into a polysilicon thin film formed on an substrate with a gate having a tapered edge which is used as a mask to form a source and a drain. An energy beam then slantingly irradiates from the side of the edge of the gate to the surface of the substrate. Thus, the source and drain are activated and, at the same time, the energy beam streams into the polysilicon thin film below the edge of the gate to activate the channel region implanted the dopant.

Abstract: A method for forming dual damascene is provided. First, a first inter-metal dielectric layer and a stop layer is formed on a substrate, and then a first photoresist pattern including a via hole and a dummy metal line is patterned and the stop layer is etched for forming via hole. Next, a second inter-metal dielectric layer is deposited and then a second photoresist pattern is patterned for forming metal line trench by etching. Afterwards, a glue layer and a metal layer are blanketed and the dual damascene structure is formed by chemical mechanical polishing.

Abstract: Cooling of densely packaged semiconductor devices is achieved by microchannels which extract heat by forced convection and the use of fluid coolant located as close as possible to the heat source. The microchannels maximize heat sink surface area and provides improved heat transfer coefficients, thereby allowing a higher power density of semiconductor devices without increasing junction temperature or decreasing reliability. In its preferred embodiment, a plurality of microchannels are formed directly in the substrate portion of a silicon or silicon carbide chip or die mounted on a ground plane element of a circuit board and where a liquid coolant is fed to and from the microchannels through the ground plane. The microchannels comprise a plurality of closed-ended slots or grooves of generally rectangular cross section. Fabrication methods include deposition and etching, lift-off processing, micromachining and laser cutting techniques.

Abstract: A thin film transistor matrix device comprises an insulating substrate, a plurality of picture element electrodes arranged in a matrix on the insulating substrate, source electrodes connected to the respective picture element electrodes, drain electrodes opposed to the respective source electrodes, operational semiconductor layers sandwiched by the source electrodes and the drain electrodes, and gate electrodes formed on the operational semiconductor layers through gate insulating films, each gate electrode being narrowed with respect to the associated gate insulating film so that side walls of the gate electrode forms a step with respect to side walls of the associated gate insulating film which is a substrate of the gate electrode.

Abstract: The present invention provides a method of forming an alloy interconnect in an integrated circuit having a dielectric layer with an opening formed therein. In an advantageous embodiment, the method comprises the steps of forming a metal alloy within the opening. The metal alloy comprises at least a first and a second metal with the first metal selected from a Group 13 metal and having a melting point substantially lower than a melting point of the second metal and the dielectric. This particular method further comprises the steps of subjecting the first and second metals to a temperature sufficient to melt the first metal and reflow the metal alloy.

Abstract: The present invention is a method and apparatus for programming a stack of segments wherein each segment includes a plurality of die which are interconnected through metal interconnects patterned on the surface of each segment. Once the segments are arranged into a stack, the stack is connected to external circuits and each segment is addressed through control lines. Electrically conductive fuses on the segments are used as an interface between the control lines and the die. Segment level programming is performed on each segment by opening the conductive fuses on the segments in a predetermined pattern in order to route the control lines to each segment such that segments are uniquely addressed. After segment level programming, circuit board programming is performed so that any defective die found in the stack is logically replaced with replacement die in the stack.

Abstract: Any one of an insulating film forming a TFT, a silicon film and a conductive film is formed by applying a solution and annealing it. In a spin coater (102), a coating solution containing a thin film component which is supplied from a solution storage section (105) is spin-coated onto a substrate. The substrate after coating the coating solution is annealed in an annealing section (103) to form a coating film on the substrate. Additional laser annealing improves one of film characteristics, i.e., crystallinity, density and adhesiveness. Application of the coating solution or a resist by an ink jet process increases utilization of the solution and permits forming a patterned coating film. Because a thin film device in accordance with the present invention is inexpensive and has a high throughput, TFT production by a production system having high utilization of the coating solution drastically reduces initial investment and production cost of a liquid crystal display device.

Abstract: Even when a contact hole is formed before thin-film resistor formation, a contact area exposed in the contact hole is prevented from damaging. A semiconductor element is formed in a silicon semiconductor substrate and an oxide film is formed on the surface of the semiconductor substrate. Then, a contact hole is formed on the oxide film and moreover, a CrSiN film serving as a thin-film resistor and a TiW film serving as a barrier metal are formed on the oxide film. The TiW film is patterned by a mask and the CrSiN film is patterned through chemical dry etching. Finally, an Al electrode is formed on the semiconductor element and the CrSiN film through the contact hole and moreover a protective film is formed thereon.