Abstract: Embodiments of the present invention provide methods for fabricating a semiconductor device with buried local interconnects. One method may include providing a semiconductor substrate with fins etched into the semiconductor substrate; forming a first set of spacers along the sides of the fins; depositing a tungsten film over the top surface of the substrate; etching the tungsten film to form a buried local interconnect; forming a set of gates and a second set of spacers; forming a source and drain region adjacent to the fins; depositing a first insulating material over the top surface of the substrate; and creating contact between the set of gates and the source and drain region using an upper buried local interconnect.

Abstract: Some embodiments include an integrated structure having a gallium-containing material between a charge-storage region and a semiconductor-containing channel region. Some embodiments include an integrated structure having a charge-storage region under a conductive gate, a tunneling region under the charge-storage region, and a semiconductor-containing channel region under the tunneling region. The tunneling region includes at least one dielectric material directly adjacent a gallium-containing material. Some embodiments include an integrated structure having a charge-trapping region under a conductive gate, a first oxide under the charge-storage region, a gallium-containing material under the first oxide, a second oxide under the gallium-containing material, and a semiconductor-containing channel region under the second oxide.

Abstract: There is provided a method of forming a tungsten nitride film on a substrate to be processed, including: forming a tungsten film by repeating a cycle of alternately supplying a tungsten chloride gas and a hydrogen-containing gas with a supply of a purge gas interposed between the supply of the tungsten chloride gas and the supply of the hydrogen-containing gas; and nitriding the tungsten film by supplying a nitrogen-containing gas.

Abstract: A display panel including a first pixel row comprising a plurality of first pixels arranged in a first direction; a second pixel row comprising a plurality of second pixels, each of the plurality of second pixels overlaps each of the plurality of first pixels in a second direction crossing the first direction, and a third pixel, the third pixel does not overlap the plurality of first pixels in the second direction, wherein the plurality of second pixels and the third pixel being arranged in the first direction; and a first vertical line comprising a first sub-line, the first sub-line is extended in the second direction and is connected to the third pixel, and a second sub-line, the second sub-line is extended from an end portion of the first sub-line in a direction away from the plurality of first pixels at a first angle relative to the second direction.

Abstract: A method for fabricating a semiconductor structure includes providing a base substrate; and forming two first fin structures and an initial isolation structure. The initial isolation structure includes a first region, located between the two first fin structures, and two second regions, each separated from the first region by a first fin structure. The method includes implanting doping ions into the initial isolation structure in the first region; and forming an isolation structure by removing a portion of the initial isolation structure. The removal rate of the initial isolation structure formed in the first region is smaller than the removal rate of the initial isolation structure formed in the two second regions. The top surface of the isolation structure is higher in the first region than in the two second regions. The method further includes forming a plurality of source/drain openings by removing a portion of the first fin structures.

Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a fin structure extending above a substrate. The fin structure includes a channel region, a portion of the channel region is made of silicon germanium (SiGe), and the silicon germanium (SiGe) has a gradient germanium (Ge) concentration. The FinFET device structure includes a gate structure formed on the channel region of the fin structure.

Abstract: Disclosed are embodiments of a lower integrated circuit (IC) package structure for a package-on-package (PoP) assembly. The lower IC package structure includes an interposer having pads to mate with terminals of an upper IC package. An encapsulant material is disposed in the lower IC package, and this encapsulant may be disposed proximate one or more IC die. An upper IC package may be coupled with the lower IC package to form a PoP assembly. Such a PoP assembly may be disposed on a mainboard or other circuit board, and may form part of a computing system. Other embodiments are described and claimed.

Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.

Abstract: To provide dummy openings having at least one of arrangement and shape determined depending on the shape of a non-effective region.

Abstract: The present application provides a power semiconductor module, including a support which carries at least one power semiconductor device, the support together with the power semiconductor device is at least partly located in a housing, the support and the power semiconductor device are at least partly covered by a sealing material, additionally to the sealing material, a protecting material is provided in the housing, the protecting material is formed from silicon gel and the protecting material at least partly covers at least one of the support, the power semiconductor device and the sealing material.

Abstract: An active matrix substrate includes a demultiplexer circuit which includes multiple TFTs. Each TFT includes a gate electrode, an oxide semiconductor layer that includes a source contact area, a drain contact area, and an area between a source and a drain that includes a channel region, a channel protection layer that covers only a portion of the area between the source and the drain, a source electrode that is brought into contact with the source contact area, and a drain electrode that is brought into contact with the drain contact area. At a cross-section in a channel length direction, of each TFT, an end portion facing toward the channel region, of one of the source and drain electrodes is brought into contact with the channel protection layer, and an end portion facing toward the channel region, of the other is positioned at a distance away from the channel protection layer.

Abstract: A method for fabricating a semiconductor substrate comprises providing a crystalline base substrate, forming an insulating layer on the crystalline base substrate and forming a trench in the insulating layer. This exposes a seed surface of the base substrate. The trench has sidewalls and a bottom. The bottom corresponds to the seed surface of the base substrate. The method further comprises growing, at a first growth step, an elongated seed structure in the trench from the seed surface of the substrate and forming a cavity structure above the insulating layer. The cavity structure covers the elongated seed structure and extends laterally to the elongated seed structure. The method comprises a further step of growing, at a second growth step, the semiconductor substrate in the cavity structure from the elongated seed structure. The invention is notably also directed to corresponding semiconductor structures and corresponding semiconductor substrates.

Abstract: A method for manufacturing an electrostatic discharge (ESD) protection device includes providing a semiconductor structure including a semiconductor substrate including a first region of a first conductivity type and a semiconductor fin on the semiconductor substrate; forming an electrode on the semiconductor fin; and performing a doping process on the semiconductor structure to forming a second region in the first region, the second region having a second conductivity type opposite the first conductivity type to form a pn junction in the semiconductor substrate. Since the pn junction is formed in the semiconductor substrate, it has a relatively large area to prevent local hot spots from occurring when a current flows through the ESD protection device, thereby reducing performance degradation of a semiconductor device.

Abstract: The present disclosure relates to an integrated circuit having a bond pad with a relatively flat surface topography that mitigates damage to underlying layers. In some embodiments, the integrated circuit has a plurality of metal interconnect layers within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has a recess with sidewalls connecting a horizontal surface of the passivation structure to an upper surface of the passivation structure. A bond pad is arranged within the recess and has a lower surface overlying the horizontal surface. One or more protrusions extend outward from the lower surface through openings in the passivation structure to contact one of the metal interconnect layers. Arranging the bond pad within the recess and over the passivation structure mitigates stress to underlying layers during bonding without negatively impacting an efficiency of an image sensing element within the substrate.

Abstract: A method of producing a lead-frame structure having two faces and exposing a treated silver surface on at least one of the two faces, the treated silver surface(s) serving the wire bonding, which yields a surface which, after applying resin to it, has excellent adhesion even under severe testing conditions, such as the IPC/JEDEC J-STD-20 MSL standard, and a method of producing a surface mount electronic device including a lead-frame or lead-frame entity and at least one semiconductor device mounted thereon, wherein the lead-frame or lead-frame entity exposes a treated silver surface on at least one of the two faces, wherein the treated silver surface(s) serve(s) the wire bonding, and wherein a resin is applied to the lead-frame or lead-frame entity, which method yields excellent adhesion of the surface of the lead-frame or lead-frame entity even under severe testing conditions.

Abstract: A method of manufacturing a semiconductor device includes in the following order: a semiconductor base body preparing step; a first trench forming step; a first insulation film forming step; a gate insulation film forming step; a gate electrode forming step; a second trench forming step of forming a second trench in the inside of a first trench by removing a center portion of the first insulation film; a second insulation film forming step of forming a second insulation film in the inside of the second trench under a condition that a first gap remain in the inside of the second trench; a shield electrode forming step of forming a shield electrode in the inside of the first gap; a shield electrode etching back step of forming a second gap; and a source electrode forming step of forming a source electrode.

Abstract: An OLED panel for a lighting device is provided. The OLED panel for a lighting device may include a substrate; a first auxiliary wiring pattern disposed on the substrate; a first electrode disposed on a substrate on which the first auxiliary wiring pattern is disposed; a passivation layer disposed on the first electrode within an area where the first auxiliary wiring pattern is disposed; a second auxiliary wiring pattern disposed on the passivation layer to form a plurality of areas partitioned from each other; an OLED light emitting structure disposed in the plurality of areas partitioned by the second auxiliary wiring pattern; a second electrode disposed on the OLED light emitting structure and the second auxiliary wiring pattern; and, an encapsulating layer disposed on the second electrode. The OLED panel for a lighting device may form the respective OLED light emitting structures in an island shape, thereby improving luminance uniformity.

Abstract: By controlling the optical thickness of the upper stacked structure disposed on the display panel, it is possible to periodically control the tristimulus value of Xr and the tristimulus value of Yg emitted from the electronic device. The optical thickness is determined by the thickness and refractive index of the upper stacked structure. This control may reduce the tristimulus value of Xr periodically or increase the tristimulus value of Yg periodically. The tristimulus value of Xr may be periodically decreased and the tristimulus value of Yg may be periodically increased at the same time.

Abstract: A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane, a first SiC region of a first conductivity type, second and third SiC regions of a second conductivity type provided between the first SiC region and the first plane, a fourth SiC region of the first conductivity type provided between the second SiC region and the first plane, a fifth SiC region of the first conductivity type provided between the third SiC region and the first plane, a gate electrode provided between the second SiC region and the third SiC region, a gate insulating layer, a sixth SiC region of the second conductivity type provided between the first SiC region and the second SiC region, and a seventh SiC region of the second conductivity type provided between the first SiC region and the third SiC region.

Abstract: The present invention generally relates to a method of making graphene and graphene devices.