Patents Examined by Matthew A Bradley
  • Patent number: 10051057
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device identifies slice error(s) associated with first storage unit(s) (SU(s)) of a first storage set that distributedly store a set of encoded data slices (EDSs) and second SU(s) of a second storage set. The computing device determines usage priority level(s) of the first SU(s) or the second SU(s) based on the slice error(s) and produces a selected storage set from the first SU(s) and the second SU(s) based on a more favorable usage priority level of the usage priority level(s) and facilitates execution of data access to at least the decode threshold number of EDSs based on the selected storage set.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Thomas D. Cocagne, Jason K. Resch, Greg R. Dhuse
  • Patent number: 10042579
    Abstract: A method, system, and computer program product for splitting IOs directed to a first LUN and a second LUN to a journal on a replication site, creating a snapshot of the first LUN, creating a snapshot of the second LUN, and applying the IO in the journal on the replication site to a copy of the snapshot of the first LUN on the replication site and a copy of the snapshot of the second LUN on the replication site to create a consistent snapshot of the first LUN and the second LUN on the replication site.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: August 7, 2018
    Assignee: EMC IP Holding Company LLC
    Inventor: Assaf Natanzon
  • Patent number: 10042853
    Abstract: A flash-optimized, log-structured layer of a file system of a storage input/output (I/O) stack executes on one or more nodes of a cluster. The log-structured layer of the file system provides sequential storage of data and metadata (i.e., a log-structured layout) on solid state drives (SSDs) of storage arrays in the cluster to reduce write amplification, while leveraging variable compression and variable length data features of the storage I/O stack. The data may be organized as an arbitrary number of variable-length extents of one or more host-visible logical units (LUNs) served by the nodes. The metadata may include mappings from host-visible logical block address ranges (i.e., offset ranges) of a LUN to extent keys, as well as mappings of the extent keys to SSD storage locations of the extents. The storage location of an extent on SSD is effectively “virtualized” by its mapped extent key (i.e.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: August 7, 2018
    Assignee: NetApp, Inc.
    Inventors: Rajesh Sundaram, Stephen Daniel, Jeffrey S. Kimmel, Blake H. Lewis
  • Patent number: 10042758
    Abstract: A high-availability storage system includes a first storage system and a second storage system. The first storage system includes a first Central Processing Unit (CPU), a first physically-addressed solid state disk (SSD) and a first non-volatile memory module that is coupled to the first CPU. Similarly, the second storage system includes a second CPU and a second SSD. Upon failure of one of the first or second CPUs, or the storage system with the non-failing CPU continues to be operational and the storage system with the failed CPU is deemed inoperational and the first and second SSDs remain accessible.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: August 7, 2018
    Assignee: Avalanche Technology, Inc.
    Inventors: Mehdi Asnaashari, Siamack Nemazie, Anilkumar Mandapuram
  • Patent number: 10042562
    Abstract: Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: August 7, 2018
    Assignee: Intel Corporation
    Inventors: Vedaraman Geetha, Henk G. Neefs, Brian S. Morris, Sreenivas Mandava, Massimo Sutera
  • Patent number: 10044807
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device dispersed error encodes a data segment to produce a set of encoded data slices (EDSs) and selects a subset of a set of storage units (SUs). Then, the computing device transmits list slice requests to the subset of the set of SUs and receive list slice responses from at least some of them. The computing device determines a highest current revision level based on list slice responses and select a revision level for the set of EDSs. The computing device generates a set of checked revision slice requests and transmit them to the set of SUs.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventor: Greg R. Dhuse
  • Patent number: 10037279
    Abstract: A data storage subsystem includes a data storage array and a host device in communication with the data storage array. Applications on servers and user terminals communicate with the host to access data maintained by the storage array. In order to enhance performance, the host includes a cache resource and a computer program including cache configuration logic which determines whether an IO received from an application is associated with a predetermined type of business process, and configures the cache resource to store data associated with the received IO where it is determined that the IO is associated with the predetermined type of business process, thereby enabling the data to be available directly from the host without accessing the storage subsystem in response to a subsequent Read request.
    Type: Grant
    Filed: June 20, 2012
    Date of Patent: July 31, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Ron Bigman, Nir Sela, Adi Hirschtein
  • Patent number: 10037272
    Abstract: A storage system includes a central processing unit (CPU) subsystem including a CPU, a physically-addressed solid state disk (SSD) that is addressable using physical addresses associated with user data, provided by the CPU, to be stored in or retrieved from the physically-addressed SSD in blocks. Further, the storage system includes a non-volatile memory module, the non-volatile memory module having flash tables used to manage blocks in the physically addressed SSD, the flash tables include tables used to map logical to physical blocks for identifying the location of stored data in the physically addressed SSD. Additionally, the storage system includes a peripheral component interconnect express (PCIe) switch coupled to the CPU subsystem and a network interface controller coupled through a PCIe bus to the PCIe switch, wherein the flash tables are maintained in the non-volatile memory modules thereby avoiding reconstruction of the flash tables upon power interruption.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 31, 2018
    Assignee: Avalanche Technology, Inc.
    Inventors: Mehdi Asnaashari, Siamack Nemazie, Anilkumar Mandapuram
  • Patent number: 10025705
    Abstract: An object-based storage system comprising a host system capable of executing applications for and with an object-based storage device (OSD). Exemplary configurations include a call interface, a physical layer interface, an object-based storage solid-state device (OSD-SSD), and are further characterized by the presence of a storage processor capable of processing object-based storage device algorithms interleaved with processing of physical storage device management. Embodiments include a storage controller capable of executing recognition, classification and tagging of application files, especially including image, music, and other media. Also disclosed are methods for initializing and configuring an OSD-SSD device.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: July 17, 2018
    Assignee: Digital Kiva Inc.
    Inventor: Paul A. Duran
  • Patent number: 10026442
    Abstract: Mechanisms are provided, in a storage system controller of a storage system, for writing data to a storage medium. The storage system controller receives a write request to write a block of data to the storage medium. The write request does not specify a location on the storage medium to which to write the block of data. The storage system controller determines a current position of a write mechanism of the storage system relative to the storage medium and determines a location on the storage medium to write the block of data based on the current position of the write mechanism. The storage system controller sends a notification to a host system identifying the location of the block of data on the storage medium as determined by the storage system controller. The writing mechanism writes the block of data to the determined location on the storage medium.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 17, 2018
    Assignee: International Business Machines Corporation
    Inventor: Toshiyuki Shiratori
  • Patent number: 10019373
    Abstract: A memory management method includes: checking shared virtual memory (SVM) support ability of at least one device participating in data access of a buffer; referring to a checking result to adaptively select an SVM mode; and allocating the buffer in a physical memory region of a memory device, and configuring the buffer to operate in the selected SVM mode.
    Type: Grant
    Filed: August 23, 2015
    Date of Patent: July 10, 2018
    Assignee: MEDIATEK INC.
    Inventors: Dz-Ching Ju, Meng-Bing Yu, Yun-Ching Li
  • Patent number: 10013168
    Abstract: Systems, apparatuses and methods may provide for communicating, by a common layer, with a local block storage system and communicating, by a subsystem layer that is communicatively coupled to the common layer, with one or more subsystems. Additionally, the common layer may be disassociated with one or more hardware specific components of the subsystem layer. In one example, the common layer may export one or more callback functions to the subsystem layer, wherein the callback functions include a registration and/or deregistration function.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: Phil C. Cayton, Jay E. Sternberg, James P. Freyensee, Dave B. Minturn
  • Patent number: 10015255
    Abstract: A computing device includes a processing module operable to generate a set of write requests regarding a set of encoded data slices. The processing module is further operable to send the set of write requests to a set of storage units, where each of at least some of the storage units of the set of storage units generates a write response. The processing module is further operable to receiving the write responses where the write responses includes at least a decode threshold number of write responses. The processing module is further operable to determine a most current revision level regarding the set of encoded data slices based on the lists of revision levels from the at least some of the storage units, and generate a set of write commit messages.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventor: Greg R. Dhuse
  • Patent number: 10007450
    Abstract: A storage controller is coupled to a plurality of storage devices, the storage controller is configured to receive a first write request of data, determine a first time when the first write request is received, specify, based on the first time, a first storage device included in the plurality of storage devices, write the data into the first storage device, receive a read request for the data, determine a second time when the read request is received, specify a second storage device included in the plurality of storage devices, wherein, in anticipation of a second write request received at the second time, the processor specifies the second storage device based on the second time, determine whether the first storage device is identical to the second storage device, and not read the data from the first storage device when the first storage device is identical to the second storage device.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: June 26, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Toshihiro Ozawa
  • Patent number: 10001921
    Abstract: A data migration method includes creating, by a first control processor that controls a first cache memory storing first cache data cached from first storage data stored in a storage, first management information including information indicating a storage location of the first cache data on the first cache memory and information indicating whether or not the first storage data has been updated in accordance with an update of the first cache data for each block of a predetermined data size in the first cache memory, when a program that accesses the first cache data migrates to a different node, transmitting, by the first control processor, the first management information to a second control processor that controls a second cache memory capable of being accessed by the program after migration to the different node.
    Type: Grant
    Filed: July 10, 2015
    Date of Patent: June 19, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Atsushi Ninomiya
  • Patent number: 9996139
    Abstract: According to one embodiment, the memory system includes a nonvolatile semiconductor memory, a data buffer, a volatile memory for storing a management table uniquely associates the user data with an address of the physical storage region of nonvolatile semiconductor memory, a controller that carries out a force quit process for writing the user data stored in a data buffer, the management table stored in volatile memory into the nonvolatile semiconductor memory, and a storage battery. The controller starts the force quit process prior to the power supply of the internal power supply regulator is switched from an external power supply to the storage battery.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: June 12, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Akihiro Kimura, Hiroki Matsushita
  • Patent number: 9990145
    Abstract: A memory system and method are provided for increasing read parallelism of translation pages. In one embodiment, a memory system is provided comprising a plurality of memory dies, where each memory die is configured with storage space for a portion of a logical-to-physical address map that is distributed among the plurality of memory dies. The memory system also comprises a controller in communication with the plurality of memory dies and configured to receive a plurality of requests to read a plurality of logical block addresses, determine which memory dies store portions of the logical-to-physical address map that contain the logical block addresses, and determine an order in which to read the portions of the logical-to-physical address map so that at least some of the portions that are stored in different memory dies are read in parallel. Other embodiments are provided.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: June 5, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Amir Shaharabany, Hadas Oshinsky
  • Patent number: 9990285
    Abstract: A data access control apparatus of an embodiment includes an update region management apparatus including an update region management unit configured to record, in response to a writing request for data from an input apparatus, management information of a first address region in which the data is stored, a reading request management unit configured to record a second address specified in a reading request from a storage apparatus and a control unit configured to receive the writing request and the reading request, and control processing of the reading request and updating of the update region management unit and the reading request management unit.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: June 5, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Seiji Maeda
  • Patent number: 9983947
    Abstract: A moving weighted average of application bandwidth is calculated based on updates to a first data storage by a first data site. A moving weighted average of transmission bandwidth is calculated based on replication of the updates to a second data storage via a second data site. A next coordinated consistency point is identified and the time remaining before the next consistency point is calculated. An amount of the updates that can be replicated before the next consistency point is determined based on the average transmission bandwidth. A prediction of an amount of additional updates that will be generated on the first data site before the next consistency point is made using heuristics based on the average application bandwidth. When update accumulation combined with the prediction exceeds the amount of updates that can be replicated before the next consistency point, pending updates are flushed to the second data storage.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Manoj P. Naik, Ravindra R. Sure
  • Patent number: 9971702
    Abstract: An example system that includes a processor and a memory device. The processor may include multiple execution units to execute instructions and a memory device coupled to the processor. The memory device stores the instructions in an unprotected region and a protected region. The processor may determine that a first exception occurred while executing a first set of instructions for an application stored in a secured page of the protected region. The processor may invoke a first subroutine to forward exception context for the first exception to a second subroutine, where the first subroutine is stored in the protected region and the second subroutine is stored in the unprotected region. The processor may invoke, by the second subroutine, a third subroutine to execute a second set of instructions associated with the exception context for the first exception.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventor: Bin Xing