Abstract: Memory having internal processors, and methods of data communication within such a memory are provided. In one embodiment, an internal processor may concurrently access one or more banks on a memory array on a memory device via one or more buffers. The internal processor may be coupled to a buffer capable of accessing more than one bank, or coupled to more than one buffer that may each access a bank, such that data may be retrieved from and stored in different banks concurrently. Further, the memory device may be configured for communication between one or more internal processors through couplings between memory components, such as buffers coupled to each of the internal processors. Therefore, a multi-operation instruction may be performed by different internal processors, and data (such as intermediate results) from one internal processor may be transferred to another internal processor of the memory, enabling parallel execution of an instruction(s).

Abstract: A method includes determining a time shift for data validity windows corresponding to a user, receiving a request for an incremental data update from the user, the user having cached data, determining that the request for the incremental data update is received within an unexpired data validity window for the cached data, wherein the data validity window is based on the determined time shift and in a case the incremental data update is received within the unexpired data validity window for the user, determining that the user is eligible for the incremental data update.

Abstract: Provided are a computer program product, system, and method for using an alias volume name for a volume to allocate space to a data set. An assignment of a plurality of volumes to a data set is maintained, wherein the volumes are configured in a storage system. A request is received to extend the data set. An alias volume name is assigned to the data set for a previously assigned volume to the data to extend the data set in response to one of the previously assigned volumes having available space to extend the data set. A base volume name is assigned to the data set for a volume not assigned to the data set in response to one of the previously assigned volumes to the data set not having available space to extend the data set.

Abstract: In one embodiment, storage arrays of solid state drives (SSDs) coupled to a node are organized as redundant array of independent disks (RAID) groups. Each storage array includes one or more segments. Each segment has contiguous free space on the SSDs. Data and metadata is organized on the SSDs with a sequential log-structured layout, with the data organized as variable-length extents of one or more logical units (LUNs). Segment cleaning is performed to clean a selected segment by moving the extents of the selected segment that contain valid data to one or more different segments so as to free the selected segment. Additional extents are written as a sequence of contiguous range write operations to the entire free segment with temporal locality to reduce data relocation within the SSDs as a result of the write operations.

Abstract: Various systems and methods can be used to perform backup to tape. For example, one method involves detecting an amount of storage in a tape drive that is available for concurrent access. The method then compares the size of a plurality of backup images to the amount of storage prior to initiating an archive operation. The method then involves adding information identifying a backup image to a list of backup images to be included in an archive operation and performing the archive operation, which involves writing the backup images to tape drive.

Abstract: Embodiments disclosed include redirecting data from a defective data entry in memory to a redundant data entry prior to data access. Related systems and methods are also disclosed. The memory is configured to receive a memory access request. The received memory access request comprises a data entry address. The memory uses the data entry address to access data stored in a data array in the memory in a first data access path. It is possible that the rows or columns in the memory may be defective as a result of a manufacturing process. In the event that a row or column at the data entry address in the data array is defective, a data entry redirection circuit redirects the memory access request to a redundant row or column in the data array prior to data access.

Abstract: In an internal register, a value for controlling operation of a flash memory is stored. A power shutoff detection register holds a value which changes when power shutoff occurs, and data stored in a specific memory cell is written in the power shutoff detection register. An EX-OR circuit compares the data stored in the specific memory cell with the value of the power shutoff detection register to thereby detect power shutoff. When power shutoff is detected, the value of the internal register is re-set. Thus, when power shutoff occurs, the flash memory can be prevented from malfunctioning.

Abstract: A secondary storage controller receives metadata that uniquely identifies a source volume of a primary storage controller. Data stored in the source volume of the primary storage controller is synchronously copied to a target volume of the secondary storage controller. The secondary storage controller receives a command from a primary host to write selected data to the source volume. In response to receiving the command at the secondary storage controller, the selected data is written to the target volume of the secondary storage controller.

Abstract: Interaction is evaluated between a computer system cache and at least one entity that submits a stream of references corresponding to location identifiers of data storage locations. The reference stream is spatially sampled by comparing a hash value of each reference with a threshold value and selecting only those references whose hash value meets a selection criterion. Cache utility values are then compiled for those references. In some embodiments, the compiled cache values may then be corrected for accuracy as a function of statistics of those location identifiers over the entire stream of references and of the sampled references whose hash values satisfied the selection criterion. Alternatively, a plurality of caching configurations is selected and the selected references are applied as inputs to a plurality of caching simulations, each corresponding to a different caching configuration. A resulting set of cache utility values is then computed for each caching simulation.

Abstract: A method for storing data in which the data to be stored is divided into a plurality of source blocks, each source block subjected to steps including defining a block key for the source block based on a random function, encrypting the source block by utilizing the defined block key, selecting at least one first storage location and one second storage location from a plurality of different available storage locations, storing control data that includes information on the defined block key at the first selected storage location, and storing encrypted data that includes information on the encrypted source block at the second selected storage location.

Abstract: One embodiment of the present invention sets forth a graphics subsystem. The graphics subsystem includes a first tiling unit associated with a first set of raster tiles and a crossbar unit. The crossbar unit is configured to transmit a first set of primitives to the first tiling unit and to transmit a first cache invalidate command to the first tiling unit. The first tiling unit is configured to determine that a second bounding box associated with primitives included in the first set of primitives overlaps a first cache tile and that the first bounding box overlaps the first cache tile. The first tiling unit is further configured to transmit the primitives and the first cache invalidate command to a first screen-space pipeline associated with the first tiling unit for processing. The screen-space pipeline processes the cache invalidate command to invalidate cache lines specified by the cache invalidate command.

Abstract: Power management functionality is described for implementing an application in an energy-efficient manner, without substantially degrading overall performance of the application. The functionality operates by identifying at least first data and second data associated with the application. The first data is considered to have a greater potential impact on performance of the application compared to the second data. The functionality then instructs a first set of hardware-level resources to handle the first data and a second set of hardware-level resources to handle the second data. The first set of hardware-level resources has a higher reliability compared to the second set of hardware-level resources. In one case, the first and second hardware-level resources comprise DRAM memory units. Here, the first set of hardware-level resources achieves greater reliability than the second set of hardware-level resources by being refreshed at a higher rate than the second set of hardware-level resources.

Abstract: A storage circuit and method are provided for propagating data values across a clock boundary between a first clock domain and a second clock domain. A storage structure is provided with at least one entry, and write circuitry performs write operations in the first clock domain, where each write operation writes a data value into an entry of the storage structure identified by a write pointer. The write circuitry alters the write pointer between each write operation. Write pointer synchronization circuitry then receives the write pointer and synchronizes the write pointer indication to the second clock domain over a predetermined number of clock cycles of the second clock domain. Read circuitry performs read operations in the second clock domain, with each read operation reading a data value from an entry of the storage structure identified by a read pointer.

Abstract: Cache utility curves are determined for different software entities depending on how frequently their storage access requests lead to cache hits or cache misses. Although possible, not all access requests need be tested, but rather only a sampled subset, determined by whether a hash value of each current storage location identifier (such as an address or block number) meets one or more sampling criteria. The sampling rate is adaptively changed so as to hold the number of location identifiers needed to be stored to compute the cache utility curves to within a set maximum limit.

Abstract: Embodiments of the invention relate to mitigating page eviction from cache memory. Pages of data in the cache are compressed, and are periodically swapped to a physical storage device to create space in the cache for additional pages. To avoid the impact of eviction latencies, an asynchronous thread scanning process scans the cache for any pages that are not committed to the storage device, decompresses a selected one of the pages, and asynchronously writes the decompressed page copy to the physical storage device. The compressed copy of the selected page remains in the cache during the asynchronous write with an indicator for the page set to convey that a replica of the page has been written to physical storage, allowing for efficient eviction from the in-memory pool at a later time.

Abstract: An apparatus and associated methodology contemplate a data storage system having a removable storage device operably transferring user data between the data storage system and another device via execution of a plurality of input/output commands. A commonality factoring module executes computer instructions stored in memory to assign commonality information to the user data. A deduplication module executes computer instructions stored in memory to combine a plurality of files of the user data (user data files) with at least one file of corresponding commonality information (commonality information file), the combined files forming a sequential data stream.

Abstract: The invention relates to an electronic memory system, and more specifically, to a system for emulating an electrically erasable programmable read only memory in a non-volatile memory device, and a method of emulating an electrically erasable programmable read only memory in a non-volatile memory device. According to an embodiment, a system for emulating an electrically erasable programmable read only memory is provided, the system including a Flash memory, wherein the Flash memory is configurable into a first region and a second region, wherein the first region is adapted to store a first class of data and the second region is adapted to store a second, different class of data.

Abstract: The disclosure is directed to a system and method of cache management for a data storage system. According to various embodiments, the cache management system includes a hinting driver and a priority controller. The hinting driver generates pointers based upon data packets intercepted from data transfer requests being processed by a host controller of the data storage system. The priority controller determines whether the data packets are associated with at least a first (high) priority level or a second (normal or low) priority level based upon the pointers generated by the hinting driver. High priority data packets are stored in cache memory regardless of whether they satisfy a threshold heat quotient (i.e. a selected level of data transfer activity).

Abstract: The various implementations described herein include systems, methods and/or devices used to avoid false negative results in Bloom filters implemented in non-volatile data storage systems. In one aspect, if an element is added to a Bloom filter using k hash functions, instead of requiring all k bits to be set before returning a positive result (e.g., indicating that the element is most likely present in the Bloom filter), the embodiments described herein return a positive result when at least k minus x (k?x) bit positions are set in the Bloom filter, where x is an integer greater than zero and less than k. In some embodiments, additional measures to avoid false negatives include performing a read check immediately after setting the k bits in the Bloom filter and/or using a conservative reading threshold voltage.

Abstract: Embodiments of the present invention are directed to a method and system for optimizing replication within a storage system utilizing multiple tiers by using tier-specific replication modes. The method includes receiving, within an electronic system having a plurality of tiers, an access request for a portion of storage associated with a first tier of the plurality of tiers and accessing a replication attribute corresponding to the first tier and also corresponding to a replication mode. The method further includes sending the access request to the portion of storage; and replicating the access request to a remote storage wherein the replicating is based on the replication mode and wherein each of the plurality of tiers have associated therewith a respective replication attribute defining a respective replication mode.