Patents Examined by Matthew Bradley
  • Patent number: 10394464
    Abstract: An electronic terminal (100) switches (500) from a normal memory access mode to a volatile memory access mode responsive to receiving user input. An open-write command is received (510) from an application to open a first file for writing. A determination (512) is made whether the first file is located in a volatile memory partition of the at least one memory. Based on determining the first file is not located in the volatile memory partition of the at least one memory, the first file is copied (516) from a normal memory partition of the at least one memory to the volatile memory partition, and the first file located in the volatile memory partition is opened (518) for writing. In contrast, based on determining the first file is located in the volatile memory partition, the first file located in the volatile memory partition is opened (520) for writing. Write commands from the application are directed (524) to the first file located in the volatile memory partition.
    Type: Grant
    Filed: November 27, 2013
    Date of Patent: August 27, 2019
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Dimitri Mazmanov, Hongxin Liang
  • Patent number: 10387330
    Abstract: Apparatuses, systems, methods, and program products are disclosed for cache replacement. An apparatus includes a cache memory structure, a processor, and memory that stores code executable by the processor. The code is executable by the processor to receive a value to be stored in the cache memory structure, identify, in response to determining that the received value is not currently stored in an entry of the cache memory structure, a least recently used (“LRU”) set of entries of the cache memory structure where the received value can be stored, and select a least frequently used (“LFU”) entry of the identified LRU set of entries for storing the received value.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: August 20, 2019
    Assignee: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD
    Inventor: Daniel J. Colglazier
  • Patent number: 10387309
    Abstract: A computing system includes multiple compute nodes that include respective processors and respective cache memories. The processors are configured to determine a default compute node in which a given data item is to be cached, to make a decision whether to cache the given data item in the default compute node or in an alternative compute node, based on cache-quality metrics that are evaluated for respective cache memories of the compute nodes, and to cache the given data item in the default compute node or in the alternative compute node, depending on the decision.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: August 20, 2019
    Assignee: Elastifile Ltd.
    Inventors: Shahar Frank, Ezra Hoch, Shai Koffman, Allon Cohen, Avraham Meir
  • Patent number: 10366005
    Abstract: Methods and systems for accessing a memory are provided. One method of accessing a memory includes generating a memory access profile for accesses to a memory array. A memory controller coupled to the memory array is configured using the generated memory access profile. After configuring the memory controller, accesses to the memory array are interleaved based on the memory access profile.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: July 30, 2019
    Assignee: NXP USA, INC.
    Inventors: Arup Chakraborty, Mazyar Razzaz, James A. Welker
  • Patent number: 10356177
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device detects memory error(s) associated with memory device(s) of set(s) of storage units (SUs). The computing device processes the memory error(s) to generate a rebuilding priority level for at least some EDS(s) and establishes an EDS scanning rate. The computing device scans the EDS(s) based on the EDS scanning rate. When an EDS error is detected, the computing device updates the rebuilding priority level to generate an updated rebuilding priority level for the at least some of the set of EDSs and facilitates generation at least one rebuilt EDS for the EDS error based on the updated rebuilding priority level.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Thomas D. Cocagne
  • Patent number: 10346069
    Abstract: A scalable approach is disclosed for processing auxiliary-copy jobs in a storage management system by using distributed media agent resources instead of a centralized storage manager. Enhanced media agents coordinate and control auxiliary-copy jobs and tap the storage manager to reserve data streams and provide job-specific metadata on demand. An enhanced storage manager may initially select a media agent as “coordinator” to coordinate auxiliary-copy jobs with any number of other media agents, which act as “controllers.” A coordinator media agent is generally responsible for obtaining data stream reservation information from the storage manager and assigning auxiliary-copy jobs to respective controller media agents, based on the components involved in the respective reserved data streams.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: July 9, 2019
    Assignee: Commvault Systems, Inc.
    Inventors: Hetalkumar N Joshi, Chandrashekar Maranna, Manoj Kumar Vijayan
  • Patent number: 10331552
    Abstract: According to one embodiment, a storage device includes a storage portion storing a first entry, the first entry includes a first translation table corresponding between a first logical address and a first physical address on a nonvolatile memory, and a first state showing that data at the first physical address is a valid as data at the first logical address, and a controller adding a second entry in the storage portion and changing the first state to a second state when receiving a command from a host, the second entry includes a second translation table corresponding between a second logical address and the first physical address, and a third state showing that the first physical address of the second translation table is referring to the first physical address of the first translation table, the second state showing that the first physical address of the first translation table is shared with the first physical address of the second translation table.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: June 25, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Isao Konuma, Norikazu Yoshida
  • Patent number: 10310770
    Abstract: This nonvolatile memory device has a blockwise-erase nonvolatile memory including a plurality of physical areas, and also has a memory controller which transmits one of a plurality of types of commands to the nonvolatile memory. After an erase command to erase one of the physical areas has been transmitted, but before a response to that erase command is received, the memory controller determines whether to suspend the ongoing erasure of the physical area, on the basis of whether there is a command to be transmitted and/or on the basis of the degree of deterioration of the physical area being erased. If the determination is affirmative, the memory controller transmits a command to the nonvolatile memory to suspend the erasure.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: June 4, 2019
    Assignee: HITACHI, LTD.
    Inventors: Masatsugu Oshimi, Junji Ogawa, Yoshihiro Oikawa
  • Patent number: 10303611
    Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register specifies a circular address mode for the loop, first and second block size numbers and a circular address block size selection. For a first circular address block size selection the block size corresponds to the first block size number. For a first circular address block size selection the block size corresponds to the first block size number. For a second circular address block size selection the block size corresponds to a sum of the first block size number and the second block size number.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: May 28, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Joseph Zbiciak
  • Patent number: 10305990
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The computing device determines to perform maintenance tasks associated with a set of memory devices of a set of storage units (SUs) of a common DSN address range. The computing device ensures that a selected number of memory devices on which the maintenance tasks are performed is less than or equal to a difference between a pillar number and a decode threshold number of dispersed error encoding parameters by which a data object is encoded and stored in the DSN. While performing the maintenance tasks, the computing device facilitates inhibiting storage of other EDSs in the set of memory devices and/or temporarily accesses at least the decode threshold number of memory devices.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas D. Cocagne, Greg R. Dhuse
  • Patent number: 10305989
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device detects a potentially adverse storage issue with a memory device of a storage unit (SU) of set(s) of storage unit(s) (SU(s)). The computing device also determines whether to transfer at least one EDSs (associated with the memory device) to another memory device for temporary storage therein. Based on a determination not to transfer, the computing device identifies at least one alternate storage location and facilitates transfer of the at least one EDSs for temporary storage therein. When the potentially adverse storage issue has subsided, the computing device facilitates transfer of the at least one EDSs back.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Niall J. McShane, Ilya Volvovski, Randy D. Pfeifer, Andrew D. Baptist, Manish Motwani, Greg R. Dhuse
  • Patent number: 10289564
    Abstract: A computer on which OSs run is coupled to the storage apparatus, the OSs include a first OS controlling access to the storage apparatus and a second OS generating a virtual computer. A logically divided computer resources are allocated to the first OS and the second OS respectively. A third OS for executing an application runs on the virtual computer. The second OS has a shared region management part managing a shared region that is a memory region used for communication between the application and the first OS. The third operating system has an agent requesting the second operating system to secure the shared region based on a request from the application and mapping the secured shared region to a guest virtual address space.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: May 14, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Yukari Hatta, Norimitsu Hayakawa, Takao Totsuka, Toshiomi Moriki, Satoshi Kinugawa
  • Patent number: 10268551
    Abstract: A method, article of manufacture, and system for cloud backups is discussed. Heterogeneous backup appliances may be deployed in a datacenter. Facades may interface these appliances with a backup management system.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: April 23, 2019
    Assignee: EMC IP Holding Company LLC
    Inventor: Steven T. Wong
  • Patent number: 10270858
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The computing device determines to perform maintenance tasks associated with a set of memory devices of a set of storage units (SUs) of a common DSN address range. The computing device ensures that a selected number of memory devices on which the maintenance tasks are performed is less than or equal to a difference between a pillar number and a decode threshold number of dispersed error encoding parameters by which a data object is encoded and stored in the DSN. While performing the maintenance tasks, the computing device facilitates inhibiting storage of other EDSs in the set of memory devices and/or temporarily accesses at least the decode threshold number of memory devices.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas D. Cocagne, Greg R. Dhuse
  • Patent number: 10254978
    Abstract: A method, and system for implementing enhanced fast full synchronization for remote disk mirroring in a computer system. A source backup copy is made locally available to a target for remote disk mirroring. Sectors are identified that are different between the source and target. A hash function is used over a block to be compared, with an adaptive number of tracking sectors per block, starting with a minimum block size.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Aaron T. Albertson, Robert Miller, Brian A. Nordland, Kiswanto Thayib
  • Patent number: 10254817
    Abstract: According to one embodiment, the memory system includes a nonvolatile semiconductor memory, a data buffer, a volatile memory for storing a management table uniquely associates the user data with an address of the physical storage region of nonvolatile semiconductor memory, a controller that carries out a force quit process for writing the user data stored in a data buffer, the management table stored in volatile memory into the nonvolatile semiconductor memory, and a storage battery. The controller starts the force quit process prior to the power supply of the internal power supply regulator is switched from an external power supply to the storage battery.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: April 9, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akihiro Kimura, Hiroki Matsushita
  • Patent number: 10257276
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device detects at least one available memory device within a storage unit (SU). The computing device identifies storage capacities of each of the memory devices within the SU and identifies a DSN address range associated with the SU. The computing device maps the DSN address range to each of the memory devices within the SU based on the storage capacities to generate a memory mapping of the memory devices within the SU. The computing device then facilitates redistribution of some EDS from a first memory device to the at least one available memory device within the SU.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Manish Motwani, Joseph M. Kaczmarek, Jason K. Resch
  • Patent number: 10250686
    Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and processing circuitry operably coupled to the interface and to the memory. The processing circuitry is configured to execute the operational instructions to perform various operations and functions. The computing device detects a potentially adverse storage issue with a memory device of a storage unit (SU) of set(s) of storage unit(s) (SU(s)). The computing device also determines whether to transfer at least one EDSs (associated with the memory device) to another memory device for temporary storage therein. Based on a determination not to transfer, the computing device identifies at least one alternate storage location and facilitates transfer of the at least one EDSs for temporary storage therein. When the potentially adverse storage issue has subsided, the computing device facilitates transfer of the at least one EDSs back.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Niall J. McShane, Ilya Volvovski, Randy D. Pfeifer, Andrew D. Baptist, Manish Motwani, Greg R. Dhuse
  • Patent number: 10248319
    Abstract: Embodiments relate to a pool of persistent storage volumes. Capacity of the volumes is managed to ensure continued operation and function of the volumes with respect to their corresponding storage pool capacity threshold(s). A background process groups the volumes within each pool into one or more clusters based on a similarity or commonality characteristic. The background process selectively performs one or more space savings techniques of a copy of a selected volume, measures impact data associated with the techniques, and maintains the data. At such time as the threshold level is approached for a storage pool, one or more space reduction actions take place on constituent volumes in view of the background process and the associated groups. The reduction action includes implementation of a space saving technique, such as compression and/or thinning, of one or more volumes in one or more clusters in an associated storage pool.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Gabriel Alatorre, Heiko Hary Ludwig, Nagapramod S. Mandagere, Yang Song
  • Patent number: 10241867
    Abstract: A method for storing and recovering data for a file system includes a write process that performs a write instruction for data that includes atomically updating corresponding data blocks and metadata-links on a storage medium. The metadata-links contain links from data blocks to parent metadata blocks and links from metadata blocks to the parent metadata blocks. A journal-less recovery process that detects one or more inconsistencies for file system blocks comprising data blocks or metadata blocks upon a system failure based on one or more comparisons of information for the file system blocks.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Prasenjit Sarkar, Mohit Saxena