Patents Examined by Matthew Bradley
  • Patent number: 9965278
    Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements for the nested loops. A steam head register stores data elements next to be supplied to functional units for use as operands. A stream template register specifies a circular address mode for the loop, first and second block size numbers and a circular address block size selection. For a first circular address block size selection the block size corresponds to the first block size number. For a first circular address block size selection the block size corresponds to the first block size number. For a second circular address block size selection the block size corresponds to a sum of the first block size number and the second block size number.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: May 8, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Joseph Zbiciak
  • Patent number: 9965409
    Abstract: The present disclosure relates to a system which includes a memory controller interface, a memory unit interface, and a correction block. The memory controller interface includes a digitally-controlled delay line (DCDL). The memory unit interface is coupled to the memory controller interface, and is configured to communicate with the memory controller interface through a first signal and a second signal. The correction block is configured to determine a result of alignment between the first signal and the second signal, and to provide a correction signal configured to align the first signal to the second signal. Other systems, devices and methods are disclosed.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: May 8, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Yu Hsu, Chien-Chun Tsai, Wen-Hung Huang
  • Patent number: 9952779
    Abstract: A controller includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a link. The processor is configured to select at least first and second memory devices for writing, and to write at least first and second data units in sequence to the first memory device over the link, while avoiding writing to any of the other memory devices until transferal of the at least first and second data units over the link has been completed, to write at least one data unit to the second memory device after transferring the at least first and second data units to the first memory device, and, in response to verifying that the first memory device is ready to receive subsequent data, to write to the first memory device at least a third data unit.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: April 24, 2018
    Assignee: APPLE INC.
    Inventors: Yoni Labenski, Roman Gindin, Etai Zaltsman, Moti Altahan, Yoram Harel, Barak Baum
  • Patent number: 9946659
    Abstract: Embodiments include a near-memory acceleration method for offloading data traversal operations from a processing element. The method is implemented at a near-memory accelerator configured to interact with each of the processing element and a memory used by the processing element. The accelerator performs the data traversal operations to chase pointers, in order to identify a pointer to data to be processed by the processing element. The data traversal operations are performed based on indications from the processing element. In addition, data needed to perform the data traversal operations are fetched by the near-memory accelerator, from the memory. The present invention is further directed to a near-memory accelerator and a computerized system comprising such an accelerator, as well as a computer program product.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: April 17, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Gero Dittmann
  • Patent number: 9934152
    Abstract: Systems and techniques relating to hardware alias detection and management in caches are described. A cache controller can receive a cache request that specifies a virtual address, which includes a virtual page number (VPN) and a page offset; access, concurrently, one or more primary tags in a slot of the cache corresponding to a primary cache index that is based on a portion of the page offset and a portion of the VPN and one or more secondary tags in one or more slots corresponding to one or more secondary cache indices that are based on the portion of the page offset and one or more variations of the portion of the VPN; and determine whether there are any primary or secondary matching ways. The controller can write store data to a primary matching way if it exists and perform an alias management operation if any secondary matching ways exist.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: April 3, 2018
    Assignee: Marvell International Ltd.
    Inventors: Richard Bryant, R. Frank O'Bleness, Sujat Jamil, Kim Schuttenberg
  • Patent number: 9933942
    Abstract: Embodiments include methods for operating a first storage system having a first number of data storage drives for enabling access to a first set of removable media. Aspects include providing a second storage system having a number K of data storage drives for enabling access to a second set of removable media and providing a set of parameters describing operational characteristics of the second storage system. Aspects also include determining an analytical model using the set of parameters, the analytical model describing the variation of average waiting time as a function of system load over a predefined range covering multiple system load regime domains and determining values of the set of parameters using the analytical model and data of the second storage system. Aspects further include using the analytical model and the values of the set of parameters for reconfiguring the first storage system.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: April 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ilias Iliadis, Yusik Kim, Slavisa Sarafijanovic, Vinodh Venkatesan
  • Patent number: 9911487
    Abstract: Embodiments of the technology relate to storing user data and metadata in persistent storage in the event of a power failure and then recovering such stored data and metadata when power is restored.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: March 6, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Nils Nieuwejaar, Jeffrey S. Bonwick
  • Patent number: 9904481
    Abstract: A scalable approach is disclosed for processing auxiliary-copy jobs in a storage management system by using distributed media agent resources instead of a centralized storage manager. Enhanced media agents coordinate and control auxiliary-copy jobs and tap the storage manager to reserve data streams and provide job-specific metadata on demand. An enhanced storage manager may initially select a media agent as “coordinator” to coordinate auxiliary-copy jobs with any number of other media agents, which act as “controllers.” A coordinator media agent is generally responsible for obtaining data stream reservation information from the storage manager and assigning auxiliary-copy jobs to respective controller media agents, based on the components involved in the respective reserved data streams.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: February 27, 2018
    Assignee: COMMVAULT SYSTEMS, INC.
    Inventors: Hetalkumar N. Joshi, Chandrashekar Maranna, Manoj Kumar Vijayan
  • Patent number: 9898375
    Abstract: A system for transmission of memory entries. The system includes a computing device that includes a memory module, a memory controller interfacing with the memory module via a memory bus, a snooping module interfacing with the memory bus, functionally in parallel to the memory module, and a high-speed interconnect, functionally connecting the snooping module to a receiving device. The memory controller is configured to write a memory entry to the memory module via the memory bus. The snooping module is configured to capture a copy of the memory entry being written to the memory module and to send the copy of the memory entry to the receiving device, via the high-speed interconnect.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: February 20, 2018
    Assignee: EMC IP Holding Company LLC
    Inventor: Jean-Philippe Fricker
  • Patent number: 9898213
    Abstract: A scalable approach is disclosed for processing auxiliary-copy jobs in a storage management system by using distributed media agent resources instead of a centralized storage manager. Enhanced media agents coordinate and control auxiliary-copy jobs and tap the storage manager to reserve data streams and provide job-specific metadata on demand. An enhanced storage manager may initially select a media agent as “coordinator” to coordinate auxiliary-copy jobs with any number of other media agents, which act as “controllers.” A coordinator media agent is generally responsible for obtaining data stream reservation information from the storage manager and assigning auxiliary-copy jobs to respective controller media agents, based on the components involved in the respective reserved data streams.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: February 20, 2018
    Assignee: COMMVAULT SYSTEMS, INC.
    Inventors: Hetalkumar N. Joshi, Chandrashekar Maranna, Manoj Kumar Vijayan
  • Patent number: 9891824
    Abstract: Embodiments relate to sub-block input/output (I/O) commands in a computer storage device. An aspect includes receiving a plurality of I/O commands on an I/O interface of the computer storage device, the computer storage device comprising a byte stream buffer module comprising a plurality of byte stream buffers, a block buffer module comprising a plurality of block buffers, and a main storage comprising a plurality of fixed-size storage blocks. Another aspect includes processing the plurality of I/O commands by the computer storage device. Another aspect includes a block write command comprising a command to write an amount of write data having a size equal to one of the plurality of a fixed-size storage block. Another aspect includes a sub-block write command comprising a command to write an amount of write data having a size that is less than a size of a fixed-size storage block.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: February 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David D. Chambliss, Lawrence Y. Chiu, Hyojun Kim
  • Patent number: 9892068
    Abstract: A memory controller (110) interfaces with one or more memory devices (120-n) having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices (120-n), the memory controller (110) automatically discovers the connectivity configuration of the one or more memory devices (120-n), including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller (110) configures the memory devices (120-n) according to the discovered connectivity and assigns unique addresses to jointly selected devices.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: February 13, 2018
    Assignee: Rambus Inc.
    Inventor: John Eric Linstadt
  • Patent number: 9880764
    Abstract: Systems, methods, and computer readable media are disclosed. A map including the number of dirty cache pages stored in the flash disk cache for each VLUN of the plurality of VLUNs on the storage system is maintained, by the storage system. A flash disk cache error requiring the storage system to take the flash disk cache offline is detected. In response to detecting the flash disk cache error a first one or more VLUNs of the plurality of VLUNs with at least one dirty cache page stored in the flash disk cache are identified by the storage system based on the map. The first one or more VLUNs are taken offline by the storage system. The flash disk cache is taken offline by the storage system. A second one or more VLUNs comprising VLUNs of the plurality of VLUNs without dirty cache pages stored in the flash disk cache are maintained online by the storage system.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: January 30, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Xinlei Xu, Jian Gao, Lifeng Yang, Geng Han, Jibing Dong, Lili Chen
  • Patent number: 9875041
    Abstract: Various examples are directed to systems and methods for backing up data. A tracking utility may receive a start request and then receive a write request directed towards the first volume. An address of the block of the volume to be modified by the write request may be recorded to a current changes list. The tracking utility may also receive a first lock request, wherein the lock request comprises an instruction to place the volume in a read-only mode. Upon receiving the first lock request, the tracking utility may copy the current changes list to a frozen changes list and clear the current changes list. Upon receiving a second lock request, the tracking utility may merge the current changes list and the frozen changes list.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: January 23, 2018
    Assignee: Acronis International GmbH
    Inventors: Andrei Redko, Stanislav Protasov, Serguei M. Beloussov, Maxim V. Lyadvinsky
  • Patent number: 9836326
    Abstract: A method and system for allocating data streams that includes receiving, at an allocator, a data stream. The data stream includes a memory address and data associated with the memory address. The method also includes examining, by the allocator, the data stream to make a determination that the data stream is a soft allocating data stream, and then sending, from the allocator based on the determination, a plurality of write probes to a plurality of caches, wherein each write probe of the plurality of write probes includes at least part of the memory address. Additionally, the method includes receiving, at the allocator in response to a write probe of the plurality of write probes, a cache line present acknowledgement from a cache of the plurality of caches, and directing, by the allocator in response to the cache line present acknowledgement, the data of the data stream to the cache.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: December 5, 2017
    Assignee: Oracle International Corporation
    Inventors: David Richard Smentek, Kathirgamar Aingaran, Sumti Jairath, Manling Yang, Serena Wing Yee Leung, Paul N. Loewenstein
  • Patent number: 9824006
    Abstract: An object-based storage system comprising a host system capable of executing applications for and with an object-based storage device (OSD). Exemplary configurations include a call interface, a physical layer interface, an object-based storage solid-state device (OSD-SSD), and are further characterized by the presence of a storage processor capable of processing object-based storage device algorithms interleaved with processing of physical storage device management. Embodiments include a storage controller capable of executing recognition, classification and tagging of application files, especially including image, music, and other media. Also disclosed are methods for initializing and configuring an OSD-SSD device.
    Type: Grant
    Filed: March 2, 2013
    Date of Patent: November 21, 2017
    Assignee: Digital Kiva, Inc.
    Inventor: Paul A. Duran
  • Patent number: 9774684
    Abstract: A method begins by a computing device generating a set of write requests regarding a set of encoded data slices and sending the set of write requests to a set of storage units, where each write request includes an encoded data slice, a corresponding slice name, and a transaction number. The method continues with each of at least some of the storage units generating a write response that includes the transaction number and a list of revision levels corresponding to the slice name. The method continues with the computing device receiving the write responses from the at least some of the storage units, determining a most current revision level based on the lists of revision levels and generating a set of write commit messages, where a write commit message includes the transaction number and a new revision level for the set of encoded data slices.
    Type: Grant
    Filed: October 6, 2015
    Date of Patent: September 26, 2017
    Assignee: International Business Machines Corporation
    Inventor: Greg Dhuse
  • Patent number: 9772775
    Abstract: In a general embodiment, a method includes storing hierarchically-organized global configuration information for each node and each tape library resource in a storage cluster to at least one memory accessible by each node of the storage cluster, the storage cluster comprising at least one tape library. The method further includes migrating and/or recalling, using the hierarchically-organized global configuration information, data to and/or from a tape cartridge pool within a tape library. The migration or recall is performed by an appropriate node of the storage cluster and in response to receiving a migration or recall request at an arbitrary node of the storage cluster.
    Type: Grant
    Filed: August 21, 2015
    Date of Patent: September 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Slavisa Sarafijanovic, Takashi Ashida, Takeshi Ishimoto, Martin Petermann, Thomas D. Weigold, Tohru Hasegawa, Mathias Bjoerkqvist, Atsushi Abe, Hiroshi Itagaki
  • Patent number: 9767014
    Abstract: A memory system for a network device is described. The memory system includes a main memory configured to store one or more data elements. Further, the memory system includes a link memory that is configured to maintain one or more pointers to interconnect the one or more data elements stored in the main memory. The memory system also includes a free-entry manager that is configured to generate an available bank set including one or more locations in the link memory. In addition, the memory system includes a context manager that is configured to maintain metadata for a list of the one or more data elements.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: September 19, 2017
    Assignee: Innovium, Inc.
    Inventors: Avinash Gyanendra Mani, Mohammad K. Issa, Neil Barrett
  • Patent number: 9760299
    Abstract: A method and system for accessing enhanced functionality on a storage device is disclosed. A hijack command is sent to the storage device that includes an identifier (such as a signature or an address). The storage device determines whether to hijack one or more subsequently commands by analyzing the subsequently commands using the identifier. For example, the storage device may analyze the subsequently received commands to determine whether the signature is in the payload of the subsequently received commands. As another example, the storage device may compare the address in the subsequently received commands with the address in the hijack command to determine whether to hijack the subsequently received commands.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: September 12, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Rotem Sela, Moshe Raz, Paul Yaroshenko