Abstract: A memory system for a network device is described. The memory system includes a main memory configured to store one or more data elements. Further, the memory system includes a parent distributed-linked list configured to store linked-list metadata. And, the memory system includes a child distributed-linked list configured to maintain list metadata to interconnect the one or more data elements stored in the main memory to generate at least a first snapshot, said linked-list metadata references the snapshot.

Abstract: Provided are a computer program product, system, and method for providing a reserved data area to use to extend a data set. A data set is configured in the volume configured in the storage. A reserved data area is configured in the storage for the volume. The reserved data area is used to extend the data set in the volume in response to there being insufficient available space in the data set. The reserved data area is used to allocate for use in the volume in response to there being no more available free space for use in the volume and if the reserved data area is available.

Abstract: Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

Abstract: An electrical device includes a main body and a detachable storage module. The main body includes a first data storage unit and is operable in plural storing modes. The detachable storage module includes a second data storage unit. When the detachable storage module is connected with the main body, the detachable storage module provides electric power to the main body and the user may select one of the plural storing modes. According to the selected storing mode, the controlling unit of the main body determines whether the data is stored in the first data storage unit or the second data storage unit. By the detachable storage module, the electrical device is more user-friendly.

Abstract: Integrated circuits may include memory interface circuitry operable to communicate with memory. The memory interface circuitry may include a memory controller and a memory interface circuit. The memory controller may fulfill memory access requests using the memory interface circuit. The memory controller may operate based on controller clock cycles of a controller clock, whereas the memory interface circuit may operate based on memory clock cycles of a memory clock. Each controller clock cycle may have a set of corresponding memory clock cycles. The memory interface circuitry may be configured using logic design computing equipment. The logic design computing equipment may identify memory timing requirements and controller latency requirements. The computing equipment may determine a command placement configuration that satisfies the timing and latency requirements. The computing equipment may configure the integrated circuit with the command placement configuration.

Abstract: Technologies are generally described herein for a reconfigurable row dynamic random access memory device. The reconfigurable row may correspond to a logically addressable row, where multiple row segments can be mapped to different physical DRAM rows. In some examples, a reconfigurable row dynamic random access memory may use a row segment activator to allow memory operation access to a row segment, while maintaining the remaining part of the same row available for other memory access operations. The reconfigurable row dynamic random access memory may be operated in various modes of operation, including a pipeline mode and a burst mode.

Abstract: A storage device and method for enabling hidden functionality are provided. In one embodiment, a storage device is provided comprising an interface a memory, and a controller. The controller is configured to receive a series of read and/or write commands to the memory from the host device. If the series of read and/or write commands received from the host device matches an expected pattern of read and/or write commands, irrespective what data is being read or written by those commands, the controller enables a special functionality mode of the storage device. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor and at least one guest operating system. The managing includes: translating from virtual addresses to intermediate physical addresses; translating from the intermediate physical addresses to physical addresses; determining reuse information for memory pages based on estimated reuse of cache lines of data stored within the memory pages; storing the determined reuse information independently from: (1) any bits used to indicate virtual addresses, (2) any bits used to indicate intermediate physical addresses, and (3) any bits used to indicate physical addresses; and using the stored reuse information to store cache lines in a selected group of multiple groups of cache lines of a first cache.

Abstract: Systems and methods for swapping out and in pinned memory regions between main memory and a separate storage location in a system, including establishing an offload buffer in an interposing library; swapping out pinned memory regions by transferring offload buffer data from a coprocessor memory to a host processor memory, unregistering and unmapping a memory region employed by the offload buffer from the interposing library, wherein the interposing library is pre-loaded on the coprocessor, and collects and stores information employed during the swapping out. The pinned memory regions are swapped in by mapping and re-registering the files to the memory region employed by the offload buffer, and transferring data of the offload buffer data from the host memory back to the re-registered memory region.

Abstract: A method and system for making global variables NUMA-aware by identifying a first and a second global variable; determining a quantity of NUMA groups of a computing device; partitioning, based on the quantity of NUMA groups, the first global variable into a first global variable array of first global variable array elements; storing each first global variable array element in a different cache line of a first plurality of cache lines of a first cache associated with a first NUMA group of the NUMA groups; partitioning, based on the quantity of NUMA groups, the second global variable into a second global variable array of second global variable array elements; and storing each second global variable array element in a different cache line of a second plurality of cache lines of a second cache associated with a second NUMA group of NUMA groups.

Abstract: A storage device and method for reallocating storage device resources based on an estimated fill level of a host buffer are disclosed. In one embodiment, a storage device receives, from a host device, a rate at which the host device stores data in its buffer and tracks an amount of data that was received from the host device. The storage device estimates a fill level of the buffer at an elapsed time using the rate, the elapsed time, and the amount of data received from the host device over that elapsed time. If the estimated fill level of the buffer is above a threshold, the storage device increases a rate of receiving data from the host device.

Abstract: A method includes determining a time shift for data validity windows corresponding to a user, receiving a request for an incremental data update from the user, the user having cached data, determining that the request for the incremental data update is received within an unexpired data validity window for the cached data, wherein the data validity window is based on the determined time shift and in a case the incremental data update is received within the unexpired data validity window for the user, determining that the user is eligible for the incremental data update.

Abstract: Systems and methods to be used by a processing element from among multiple computing resources of a computing system, where communication between the computing resources is carried out based on network on a chip architecture, to send first data from memory registers of the processing element and second data from memory of the computing system to a destination processing element from among the multiple computing resources, by sending the first data to a memory controller of the memory along with a single appended-read command.

Abstract: Address translation circuitry and a method of operating such a translation circuitry are provided. The address translation circuitry is configured to receive a first address used in a first addressing system and to translate it into a second address used in a second addressing system. Translation pipeline circuitry has plural pipeline stages configured to translate the first address into the second address over the course of the plural pipeline stages. Address comparison circuitry is configured to identify an address match condition when a received first address at least partially matches a previously received first address. Insertion circuitry is configured to determine a stage of progress of the previously received first address in the plural pipeline stages and to cause content of the stage of progress of the previously received first address to be unchanged at a next pipeline cycle when the address comparison circuitry identifies the address match condition.

Abstract: A control method of a memory device, a memory device and a memory system are provided. The memory system includes a memory control unit and a memory die. The memory die performs a data access operation asynchronously with respect to a system clock according to address information and an access signal generated from the memory control unit. When operating in a read mode, the memory die generates a data tracking signal according to a memory internal read time which is an elapsed time for data to be read to be read out from the memory die. The memory control unit and the memory die obtain required data according to respective data tracking signals transmitted therebetween. The control method defines an asynchronous memory interface protocol which realizes reliable and high speed data transmission.

Abstract: The present principles relate to a method of imprinting new identifying information to a flash memory device. The method includes receiving, at a flash memory, a new identifying information to be written to the flash memory, the flash memory having a plurality of sectors and a pointer associated therewith, the plurality of sectors including a locked first sector that includes previously written identifying information, the pointer including an address of the first sector; writing the new identifying information to a second sector of the plurality of sectors, the second sector being open and lockable; and locking the second sector.

Abstract: A method is used to build a concurrent data structure in the form of a ranked register based on a Compare-And-Swap (CAS) functionality and an according ranked register, to allow reliable access of shared data within a storage by multiple clients. Read and write operations are defined within the ranked register. The read operation takes a rank as argument and returns a rank-value pair. The write operation takes a rank-value pair as argument and returns either commit or abort. The read operation returns a rank-value pair that was written in a previous write operation.

Abstract: A non-volatile memory device includes a memory core storing data to be output from the memory core according to an external clock signal, an input buffer receiving the external clock signal and providing an input clock signal, and a synchronization circuit including a delay circuit and configured to receive the input clock signal, provide an output clock signal, and synchronize the output clock signal to the external clock signal. The device further includes a data strobe output buffer receiving the output clock signal and providing a data strobe signal having a signal delay configurable relative to the external clock signal, a clocked circuit element receiving the data and the output clock signal and outputting the data in synchronism with the output clock signal, and a delay control circuit providing a delay control signal to the delay circuit to modify the signal delay of the data strobe signal.

Abstract: According to one embodiment, the memory system includes a nonvolatile semiconductor memory, a data buffer, a volatile memory for storing a management table uniquely associates the user data with an address of the physical storage region of nonvolatile semiconductor memory, a controller that carries out a force quit process for writing the user data stored in a data buffer, the management table stored in volatile memory into the nonvolatile semiconductor memory, and a storage battery. The controller starts the force quit process prior to the power supply of the internal power supply regulator is switched from an external power supply to the storage battery.

Abstract: A system and method for providing a print formatted string wherein a format object is created for a format string a format string having a set of format specifiers, an amount of memory to allocate to a string buffer for the format object is determined, and the determined amount of memory is allocated to the string buffer. For each set of parameter values received with the format object, where each parameter value corresponds to a format specifier in the format string, a determination is made whether the determined amount of memory for the string buffer is sufficient to hold the set of input parameter values in accordance with the format string. If the determined amount of memory is insufficient, an amount of memory sufficient for the set of input parameter values in accordance with the format string is re-determined, and the string buffer is reallocated to the re-determined amount of memory.