Abstract: Sequentially scanned digital input signals are applied to the controller to derive output signals which are formed of the sum of scanned values of the signals weighted with selected coefficients. The weighting with the coefficients is carried out by use of coefficients stored in a table, for example a read-only memory (3, 16); the sum of the respectively weighted signals is then formed in a sequential adder (4, 5; 23, 26, 24, 25). Multiplex operation of respective signals, associated with selected coefficient addresses, can be obtained.

Abstract: A system for processing data matrices such as images and spatially related data includes a plurality of neighborhood processing units connected in a linear chain with direct data communication links between adjacent processing units. A sequence of instructions are sent to the processing units by a single controller, where all neighborhood processing units in the system receive the same instruction at any given cycle in the instruction sequence. The width of the data matrix array is the same as a number of processors, so that there is one processor per column in the data matrix. The memory associated with each processor is external and large enough to hold the entire image or data matrix. The processors are able to operate arithmetically in a serial or parallel mode, where an efficient means is provided to transpose 8.times.8 bit submatrices between the two modes. An indirect addressing means is provided which operates on byte-wide memories external to the processing unit.

Abstract: A data processing security device, attached to computing equipment, inserts labels into a data stream that indicate security controls for the data. The security device may also be configured to detect security labels within a data stream and inhibit the flow of data. It also may replace data within a data stream if it detects labeled fields which indicate that privacy should be imposed.

Abstract: A basic input and output system program, (BIOS) includes a 16-bit interface hard disk controller, (HDC) control routine and an 8-bit interface HDC control routine, and also includes an automatic HDC type determination routine. The 16-bit interface HDC has an inherent I/O address (I/O port), but the 8-bit interface HDC has no inherent I/O address (I/O port). By utilizing this fact, a CPU writes specified data at the I/O address inherent to the 16-bit interface HDC. The CPU then reads out the data from the I/O address, and compares the read data with the written data. If a coincidence is obtained, the CPU determines that the 16-bit interface HDC is used, and sets up a 16-bit interface HDC control routine. On the other hand, if no coincidence is obtained, the CPU determines that the 8-bit interface HDC is used, and sets up an 8-bit interface HDC control routine.

Abstract: A circuit for tying down a computer bus when the bus is idle by monitoring a series of signals which indicate whether the bus is being used and storing the data signal values on the bus, such that when the bus goes idle the last data value on the bus immediately prior to the bus becoming idle is applied to the bus to hold it at its last known signal value. When a new bus operation is initiated the bus is automatically released for normal operation.

Abstract: A memory management unit in which logical addresses are translated into physical addresses is provided that comprises a segment register section that is composed of a plurality of segment registers; a segment address decoder for selecting a desired segment register in the segment register section; and an effective-address selection register from which an effective address for the desired segment register is fed to the segment address decoder. A part of the logical address is used as the effective address and the remaining part of the logical address is used as an expanded part of the physical address.

Abstract: An I/O structure for use in a digital data processing system of the type in which system components including a processor and a system memory are connected by a system bus. The I/O structure includes a system bus interface connected to the system bus, a synchronous satellite processing unit (SPU) bus connected to the system bus interface, one or more satellite processing units (SPUs) connected to the SPU bus, and peripheral devices attached to the satellite processing units. Each SPU has three main components: control logic including a microprocessor for controlling the SPU, a device adapter specific to the peripheral device for controlling the peripheral device and transferring data between the peripheral device and the SPU, and an interface unit connected to the control logic and the device adapter for providing I/O communications to the SPU bus and responding to I/O communications on the SPU bus. The I/O communications fall into two classes: communications to SPUs and communications to system components.

Abstract: A digital computer system has a central processor unit (CPU). A computer program, entered into the digital computer system for execution thereof, has a program code word embedded at an arbitrary location therein. An addressable programmable array of logic (PAL) is operatively connected to the CPU for receiving a READ signal originated by the CPU at the address of the PAL, the PAL being programmed to output a portion of a preset array code word in a response to the READ signal, and to output the remainder of the array code word in segments in response to subsequent READ signals at the same address. A data bus, connected to receive and transmit the portion and remainders of the array code word to the CPU for comparison with the program code word. The program code word and the array code word are compared and, if identical permit use of the program and do not permit use when the program code word and the array code word are not identical.

Abstract: A serial protocol register and an initialization counter are configured to initialize (program) a RAM array. The register is configured to receive, in serial format, an initial address to be loaded into the counter. Also, the register is configured to receive, in serial format, a series of machine states (data words), each to be stored in the RAM array. In addition, the register is configured to clock the counter following each received machine state. The counter is configured to develop a series of addresses, each for accessing the RAM array to store in the array a corresponding one of the machine states.

Abstract: An expansible fixed disk drive data storage subsystem enables attachment of multiple bus-level interface fixed disk drives to a host computer at a single us-level interface fixed disk drive input/output logiical address location.

Abstract: A cellular network assignment processor (10) for solving optimization problems utilizing a neural network architecture having a matrix of simple processing cells (12) that are highly interconnected in a regular structure. The cells (12) accept as input, costs in an assignment problem. The position of each cell (12) corresponds to the position of the cost in the associated constraint space of the assignment problem. Each cell (12) is capable of receiving, storing and transmitting cost values and is also capable of determining if it is the maximum or the minimum of cells (12) to which it's connected. Operating on one row of cells (12) at a time the processor (10) determines if a conflict exists between selected connected cells (12) until a cell (12) with no conflict is found in each row. The end result is a chosen cell (12), in each row, the chosen cells (12) together representing a valid solution to the assignment problem.

Abstract: A machine translation system has a display section, an original storage section for storing an original sentence, a dictionary storing linguistical information necessary for translation processing, a translation processing section for translating the original sentence for each predetermined processing unit to obtain a translated sentence, a translation storage section for storing the translated sentence, an edit processing section for executing edit processing for the original and translated sentences, and an input section for inputting instruction information. In addition, the system has a display control section for realizing a first display mode for displaying the original and translated sentences respectively on original and translation display sections of a display screen of the display section, a second display mode for mainly displaying the original sentences on the display screen, and a third display mode for mainly displaying the translated sentences on the display screen.

Abstract: An apparatus for capturing data outputted by a data processing unit includes an interface unit for generating a strobe pulse for each data word outputted, a timer for measuring the elasped time between the occurrence of two consecutive data words and a DMA controller for storing the data words together with the elapsed time data words in a remote storage unit. A time-out circuit insures that the time measured is between the occurrence of the first and second data words of each pair of data words.

Abstract: A bus-to-bus interface circuit maps a portion of the address space of each bus to a corresponding portion of the address space of the other bus. When a computer processor one one bus attempts to read or write access a mapped address, the bus interface circuit obtains control of the other bus and read or write accesses a corresponding address on the other bus. The interface circuit permits a bus master on the first bus to lock both buses so that it may perform several bus-to-bus data read or write operations without having to re-arbitrate for control of either bus after each operation.

Abstract: A computer interconnect coupler has channel transmitters and logic and channel receivers and logic circuitry for the routing of messages from the channel receivers which are addressed to the channel transmitters. When a message is received by a channel receiver, the channel receiver stores the beginning portion of the message in a first-in-first-out buffer, and sends a route message request to central switch logic. If the destination transmitter or receiver is busy, the central logic places the message request on a destination queue and returns a signal to the requesting source transmitter to turn on a flow control signal which is transmitted back to the data processing device having originated the message. Any message addressed to this data processing device, however, is inserted into the flow control carrier with pauses both before and after the message, and provisions are also made to allow the data processing device to return an ackowledgement responsive to the incoming message.

Abstract: A bus arbitration system is disposed between a plurality of devices for granting use of a bus having a data bus size larger than a port size of each of the plurality of devices. A plurality of partial buses are made from the full size bus. Each of the partial buses has a data bus size equal to the corresponding port size of the devices, and each of the devices is connected to one of the partial buses through a corresponding port unit. An arbitration between the plurality of devices for granting use of the bus is carried out for each partial bus through the corresponding port unit.

Abstract: In a data processing system for management of a relational data base stored among a plurality of disc storage units, a method and apparatus for horizontally partitioning a physical page on the basis of tuples includes a master processor, a master disc storage unit coupled to the master processor, a plurality of slave processors controlled by the master processor, and a plurality of slave disc storage units, one coupled to each of the slave processors. The master disc storage unit stores, in the form of a B-tree structure, a clustered index for either an attribute or a relation to be processed in the relational data base. The plurality of slave disc storage units store divisionally a relation in the data base which is partitioned on the basis of a page for a clustered index thereof in such a manner that the plurality of slave processors may execute, in parallel, a plurality of processings on a cluster of tuples, as defined in their range in connection with a given key value of the clustered index.

Abstract: A high speed computer that permits the partitioning of a single computer program into smaller concurrent processes running in different parallel processors. The program execution time is divided into synchronous phases, each of which may require a shared memory to be configured in a distinct way. At the end of each execution phase, the processors are resynchronized such that the composite system will be in a known state at a known point in time. The computer makes efficient use of hardware such that n processors can solve a problem almost n times as fast as a single processor.

Abstract: The buffer device array includes plural buffer devices connected to a bus, wherein the buffer devices hold the respective device addresses and device selection signals in the course of a data transfer operation and subsequently the device addresses and device selection signals held in the devices are used for inspecting devices with respect to whether they can be used for the next data transfer operation, thus enabling the data transfer operation and checking of device status for the next data transfer to be performed in a pipeline fashion and significantly increasing the efficiency of the data transfer operation and of the overall bus utilization.

Abstract: An improved keyboard interface is provided for use with personal computers. A received scancode from the keyboard is made available at a port which may be repeatedly inspected by the CPU. The scancode data remains available until explicitly cleared by the CPU, or until a preestablished time-out interval has expired.