Abstract: The current disclosure is directed towards efficiently generating random sequences on a large-scale peer-to-peer network. In one example, the disclosure provides for selecting a first node based on a block generation order, where the first node is selected to generate a current block, adding a first signature share of the first node to the current block, adding at least a second signature share from a previously selected node to the current block, generating a random sequence based on the first signature share and the second signature share, adding the random sequence to the current block, and publishing the current block to a blockchain maintained by a node pool. In this way, a random sequence may be generated on-chain, with linear messaging complexity, without relying on a single trusted party/apparatus, which may thereby decrease a probability of any single party controlling the random sequence produced.

Abstract: Certain aspects of the present disclosure are directed to methods and apparatus for circular floating point addition. An example method generally includes obtaining a first floating point number represented by a first significand and a first exponent, obtaining a second floating point number represented by a second significand and second exponent, and adding the first floating point number and the second floating point number using a circular accumulator device.

Abstract: Example devices are described that include a computational unit configured to process first set of data bits encoding a first numerical value and a second set of data bits encoding a second numerical value. The computational unit includes a bit-stream generator configured to generate bit combinations representing first and second bit sequences that encode the first and second numerical values, respectively, based on a proportion of the data bits in the sequence that are high relative to the total data bits. The first bit sequence is generated using a first Sobol sequence source, and the second bit sequence is generated using a second Sobol sequence source different from the first Sobol sequence source. The device also includes computation logic configured to perform a computational operation on the bit combinations and produce an output bit-stream having a set of data bits indicating a result of the computational operation.

Abstract: An adder circuit inhibiting overflow is provided. A first memory, a second memory, a third memory, and a fourth memory are included. A step of supplying first data with a sign to the first memory and supplying the first data with a positive sign stored in the first memory, to the second memory; a step of supplying the first data with a negative sign stored in the second memory, to the third memory; a step of generating second data by adding the first data with a positive sign stored in the second memory and the first data with a negative sign stored in the third memory; and a step of storing the second data in the fourth memory are included. When the second data stored in the fourth memory are all second data with a positive sign or all second data with a negative sign, all the second data stored in the fourth memory are added.

Abstract: A tile of an FPGA includes a multiple mode arithmetic circuit. The multiple mode arithmetic circuit is configured by control signals to operate in an integer mode, a floating-point mode, or both. In some example embodiments, multiple integer modes (e.g., unsigned, two's complement, and sign-magnitude) are selectable, multiple floating-point modes (e.g., 16-bit mantissa and 8-bit sign, 8-bit mantissa and 6-bit sign, and 6-bit mantissa and 6-bit sign) are supported, or any suitable combination thereof. The tile may also fuse a memory circuit with the arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased.

Abstract: In one embodiment, a method includes receiving a request for an operation to be performed; determining that the operation is associated with a machine-learning algorithm, and in response, route the operation to a computing circuit; performing, at the computing circuit, the operation, including: determining a linear domain product of a first log-domain number and a second log-domain number associated with the operation based on a summation of the first log-domain number and the second log-domain number and output a third log-domain number approximating the linear domain product of the first log-domain number and the second log-domain number; converting the third log-domain number to a first linear-domain number; summing the first linear-domain number and a second linear-domain number associated with the operation, and output a third linear-domain number as the summed result.

Abstract: A computer-implemented optimization problem arithmetic method includes, receiving a combinatorial optimization problem, selecting a first arithmetic circuit from among a plurality of arithmetic circuits based on a scale or a requested accuracy of the combinatorial optimization problem and a partition mode that defines logically divided states of each of the plurality of arithmetic circuits, and causing the first arithmetic circuit to execute an arithmetic operation of the combinatorial optimization problem.

Abstract: A pseudorandom number is obtained from a pseudorandom number generator. A first register input is created using the pseudorandom number. The first register input is inserted into a shift register which also comprises a second register input. A first digit of the first register input and a second digit of the second register input are selected from the shift register. A seed is created using the first digit and the second digit. The seed is input into the pseudorandom number generator. A newly generated pseudorandom number is obtained from the pseudorandom number generator.

Abstract: A processing-in-memory (PIM) device includes a multiplication/accumulation (MAC) operator. The MAC operator includes a multiplying block and an adding block. The multiplying block includes a first multiplier and a second multiplier. The first multiplier performs a first multiplying calculation of first half data of first data and first half data of second data. The second multiplier performs a second multiplying calculation of second half data of the first data and second half data of the second data. The adding block performs an adding calculation of first multiplication result data outputted from the first multiplier and second multiplication result data outputted from the second multiplier. The MAC operator receives a test mode signal having a first level to perform a test operation for the multiplying block.

Abstract: A linear system solving method, system, and computer program product, include calculating a matrix factorization for a matrix in a pair of matrices, in a form of a lower, a diagonal, an upper (LDU) decomposition, solving a first expression for a first value using a substitution module to create a first result, dividing the first result by values stored in the diagonal of the matrix to obtain a second result, and solving a second expression for a second value where a processing of the diagonal is skipped by using the second result.

Abstract: The invention is notably directed at a device for high-dimensional computing comprising an associative memory module. The associative memory module comprises one or more planar crossbar arrays. The one or more planar crossbar arrays comprise a plurality of resistive memory elements. The device is configured to program profile vector elements of profile hypervectors as conductance states of the resistive memory elements and to apply query vector elements of query hypervectors as read voltages to the one or more crossbar arrays. The device is further configured to perform a distance computation between the profile hypervectors and the query hypervectors by measuring output current signals of the one or more crossbar arrays. The invention further concerns a related method and a related computer program product.

Abstract: An in-memory computation device including a memory array, p×q analog to digital converters (ADCs) and a ladder adder is provided. The memory array is divided into p×q memory tiles, where p and q are positive integers larger than 1. Each of the memory tiles has a plurality local bit lines coupled to a global bit line respectively through a plurality of bit line selection switches. The bit line selection switches are turned on or cur off according to a plurality of control signals. The memory array receives a plurality of input signals. The ADCs are respectively coupled to a plurality of global bit lines of the memory tiles. The ADCs respectively convert electrical signals on the global bit lines to generate a plurality of sub-output signals. The ladder adder is coupled to the ADCs, and performs an addition operation on the sub-output signals to generate a calculation result.

Abstract: An apparatus and method are provided for saturation prevention of a current integrator in a Resistive Processing Unit-based (RPU-based) accelerator. The apparatus includes a set of hardware switches. The apparatus further includes a voltage generator, operatively coupled between an input terminal and an output terminal of the current integrator, reducing a magnitude of an output voltage at the output terminal of the current integrator during a current integration operation by selectively applying a non-zero initial voltage to the current integrator prior to the current integration operation, responsive to an operating state of the set of hardware switches.

Abstract: A method includes dividing a fraction of a floating point result into a first portion and a second portion. The method includes outputting a first normalizer result based on the first portion during to a first clock cycle. The method includes storing a first segment of the first portion during to the first clock cycle. The method includes outputting a first rounder result based on the first normalizer result during to the first clock cycle. The method includes outputting a second normalizer result based on the second portion during to a second clock cycle. The method includes outputting a second rounder result based on the second normalizer result and the first segment during to the second clock cycle.

Abstract: A Random-Number Generator (RNG) includes a first plurality of High-Frequency (HF) clock generators, a second plurality of Low-Frequency (LF) clock generators, a third plurality of Digital Random-Number Generator circuits (DRNGs), and a multiplexer. The HF clock generators are configured to generate respective HF clock signals in a first frequency range. The LF clock generators are configured to generate respective LF clock signals in a second frequency range, lower than the first frequency range. Each DRNG is configured to derive a respective random-bit sequence from (i) a respective HF clock signal taken from among the HF clock signals and (ii) a respective LF clock signal taken from among the HF clock signals. The multiplexer is configured to produce an output sequence of random bits from random-bit sequences generated by the DRNGs.

Abstract: Preparation and execution of quantized scaling may be performed by operations including obtaining an original array and a scaling factor representing a ratio of a size of the original array to a size of a scaled array, determining, for each column of the scaled array, a horizontal coordinate of each of two nearest elements in the horizontal dimension of the original array, and, for each row of the scaled array, a vertical coordinate of each of two nearest elements in the vertical dimension of the original array, calculating, for each row of the scaled array and each column of the scaled array, a linear interpolation coefficient, converting each value of the original array from a floating point number into a quantized number, converting each linear interpolation coefficient from a floating point number into a fixed point number, storing, in a memory, the horizontal coordinates and vertical coordinates as integers, the values as quantized numbers, and the linear interpolation coefficients as fixed point numbers

Abstract: An integrated circuit with specialized processing blocks are provided. A specialized processing block may be optimized for machine learning algorithms and may include a multiplier data path that feeds an adder data path. The multiplier data path may be decomposed into multiple partial product generators, multiple compressors, and multiple carry-propagate adders of a first precision. Results from the carry-propagate adders may be added using a floating-point adder of the first precision. Results from the floating-point adder may be optionally cast to a second precision that is higher or more accurate than the first precision. The adder data path may include an adder of the second precision that combines the results from the floating-point adder with zero, with a general-purpose input, or with other dot product terms. Operated in this way, the specialized processing block provides a technical improvement of greatly increasing the functional density for implementing machine learning algorithms.

Abstract: An arithmetic logic unit, comprising an addition unit for determining a sum of a first input and a second input; and a logarithmic addition unit for determining an output using the sum and a third input. The output is a multiply-accumulate output represented in a logarithmic domain when the first, second and third inputs are represented in the logarithmic domain.

Abstract: A device for providing a random number generator is provided. The device may include a true random number generator, at least one deterministic random number generator, and an exclusive OR logic function. The TRNG has an output and the at least one DRNG has an output. The exclusive OR logic function has a first input coupled to the output of the TRNG and a second input coupled to the output of the at least one DRNG, and an output for providing a random number. The TRNG and the at least one DRNG may include separate and independent entropy sources. A method for generating a random number is also provided.

Abstract: An execution unit for a processor, the execution unit comprising: a look up table; a preparatory circuit configured to determine an index value in dependence upon the operand and search the look up table using the index value to locate an entry comprising a natural logarithm associated with the index value; control circuitry configured to provide a first value determined in dependence upon the operand and a second value determined in dependence upon the operand as inputs to at least one multiplier circuit of the execution unit so as to evaluate terms of a Taylor series expansion of a natural logarithm, wherein the control circuitry is configured to provide the natural logarithm associated with the index value and the terms of the Taylor series expansion as inputs to at least one addition circuit so as to generate a mantissa of a natural logarithm of the operand.