Abstract: An improved integrator for use in physical analog-computing systems is disclosed, featuring real-time dynamic amplitude scaling schemas that make use of an injected correction factor responsive to a contemporaneous change in an input dynamic-amplitude-scaling compensation factor. The injected correction factor is designed to reduce or eliminate transient output perturbations due to the amplitude scaling change. The disclosures discussed have real-world applications for physical analog computers and hybrid computers used to control and manage many types of industrial-control systems.

Abstract: The present invention provides a calculator comprising number keys for digits one through nine, a NULL key, a first additional number key configured to represent 3.663, and a second additional fixed value number key configured to represent 6.336. The number keys are operatively coupled to processor configure to execute mathematical functions. The calculator can be a stand-alone device, or be executed within a cell phone, tablet, or other general purpose computer.

Abstract: A computing device to implement fast floating-point adder tree for the neural network applications is disclosed. The fast float-point adder tree comprises a data preparation module, a fast fixed-point Carry-Save Adder (CSA) tree, and a normalization module. The floating-point input data comprises a sign bit, exponent part and fraction part. The data preparation module aligns the fraction part of the input data and prepares the input data for subsequent processing. The fast adder uses a signed fixed-point CSA tree to quickly add a large number of fixed-point data into 2 output values and then uses a normal adder to add the 2 output values into one output value. The fast adder uses for a large number of operands is based on multiple levels of fast adders for a small number of operands. The output from the signed fixed-point Carry-Save Adder tree is converted to a selected floating-point format.

Abstract: A computer-implemented optimization problem arithmetic method includes receiving a combinatorial optimization problem, determining, based on scale or a requested accuracy of the combinatorial optimization problem, a partition mode and an execution mode, the partition mode defining a logically divided state of an arithmetic circuit, the execution mode defining a range of hardware resources to be utilized in arithmetic operation for each of partitions generated by logically dividing the arithmetic circuit, and causing the arithmetic circuit to execute arithmetic operation of the combinatorial optimization problem in accordance with the determined partition mode and the determined execution mode.

Abstract: A calculation apparatus according to an embodiment includes matrix multiplication circuitry, time evolution circuitry, management circuitry, and output circuitry. The matrix multiplication circuitry calculates N second intermediate variables at a first time point by matrix multiplication between N (N>=2) first intermediate variables at the first time point and a preset coefficient matrix in N rows and N columns. The time evolution circuitry calculates N first variables at a second time point and N first intermediate variables at the second time point, the second time point being a time point following one sampling period after the first time point. The management circuitry increments time point from a start time point for each sampling period and controls the above circuitry to perform a process for each time point. The output circuitry outputs N first variables at a preset end time point.

Abstract: A memory device includes a memory core that stores data, an access controlling unit that controls an access to the memory core, and a random number generating unit that generates a random number based on an unstable factor related to an access operation to the memory core performed by the access controlling unit.

Abstract: A multiplier circuit is described in which sub-products calculated in a first stage of a carry-save adder (CSA) network are output early, processed by applying a processing function, and re-injected into a subsequent stage of the CSA network to add the processed sub-products. This allows a CSA network provided for multiplication operations to be reused for operations which require sub-products to be processed and added, such as floating-point dot product operations performed on floating-point values represented in bfloatl6 format.

Abstract: Compute-in memory circuits and techniques are described. In one example, a memory device includes an array of memory cells, the array including multiple sub-arrays. Each of the sub-arrays receives a different voltage. The memory device also includes capacitors coupled with conductive access lines of each of the multiple sub-arrays and circuitry coupled with the capacitors, to share charge between the capacitors in response to a signal. In one example, computing device, such as a machine learning accelerator, includes a first memory array and a second memory array. The computing device also includes an analog processor circuit coupled with the first and second memory arrays to receive first analog input voltages from the first memory array and second analog input voltages from the second memory array and perform one or more operations on the first and second analog input voltages, and output an analog output voltage.

Abstract: Methods are disclosed for manufacturing a true random number generator (TRNG), wherein the TRNG includes a cavity filled with tritium and an electronic sensor constructed to detect energy from the decay of the tritium. One method includes (a) forming the cavity by bonding an enclosing structure to the sensor or adjacent to the sensor such that a portion of the sensor forms an inner surface of the cavity, (b) injecting the tritium gas into the cavity via one or more ports in the enclosing structure, and (c) sealing the one or more ports. Another method includes (a) applying a drop of tritiated water or tritiated gel to a surface of the electronic sensor, and (b) applying epoxy over the drop of tritiated water or tritiated gel (prior to step (b), the surface of the electronic sensor may be cooled sufficiently to freeze the drop of tritiated water or tritiated gel).

Abstract: Implementations disclosed describe a system and a method to execute a virtual machine on a processing device, receive a request to access a memory page identified by a guest virtual memory address (GVA) in an address space of the virtual machine, translate the GVA to a guest physical memory address (GPA) using a guest page table (GPT) comprising a GPT entry mapping the GVA to the GPA, translate the GPA to a host physical address (HPA) of the memory page, store, in a translation lookaside buffer (TLB), a TLB entry mapping the GVA to the HPA, modify the GPT entry to designate the memory page as accessed, detect an attempt by an application to modify the GPT entry; generate, in response to the attempt to modify the GPT entry, a page fault; and flush, in response to the page fault, the TLB entry.

Abstract: Provided are a method and system for using a non-linear feedback shift register (NLFSR) for generating a pseudo-random sequence with at least near-maximal length for n number of stages, where a maximal length is 2n?1. The method may include selecting n, where n requires more than two taps in maximal length linear feedback shift registers; and generating, for the selected n-stage register, a pseudo-random sequence using a feedback logical operation of only a first logic gate and a second logic gate. Two suitable non-end taps are inputs for the first logic gate, an output of the first logic gate and an end tap are inputs for the second logic gate, and an output of the second logic gate is used as feedback to a first stage of the n-stage register.

Abstract: According to the embodiments, a semiconductor device includes: an adder configured to generate positive multiple data of the multiplicand which is used for a plurality of the multiplication in plurality and does not include a value of 2n (n is a positive integer) of the multiplicand; a Wallace tree circuit provided in each of the multiplier circuits and configured to operate a sum of a plurality of partial products by using a plurality of adders; and a selection circuit provided in each of the multiplier circuits and configured to select, according to a plurality of bits selected from the multiplier, data falling in a multiple of one of the multiplicand, data of 2n of the multiplicand, and the positive multiple data from the adder in order to output as one partial product of the plurality of partial products to the Wallace tree circuit.

Abstract: The example embodiments of the invention notably are directed to a computer-implemented method for assessing distances between pairs of histograms. Each of the histograms is a representation of a digital object; said representation comprises bins associating weights to respective vectors. Such vectors represent respective features of said digital object. This method basically revolves around computing distances between pairs of histograms. That is, for each pair {p, q} of histograms p and q of said pairs of histograms, the method computes a distance between p and q of said each pair {p, q}. In more detail, said distance is computed according to a cost of moving p into q, so as to obtain a flow matrix F, whose matrix elements Fi,j indicate, for each pair {i,j} of bins of p and q, how much weight of a bin i of p has to flow to a bin j of q to move p into q. This is achieved by minimizing a quantity ?i,jFi,j·Ci,j, where Ci,j is a matrix element of a cost matrix C representing said cost.

Abstract: A user programmable integrated circuit includes a user-programmable routing network including a plurality of interconnect conductors selectively couplable to one another by user-programmable elements. A plurality of matrix vector multipliers, each have a plurality of word lines, each word line coupled to a different first one of the one of the interconnect conductors of the user-programmable routing network, the word lines forming intersections with a plurality of summing bit lines, a programmable Vt transistor at each intersection having a gate connected to the intersecting word line, a source connected to a fixed potential and a drain connected to the intersecting summing bit line. A charge-to-pulse-width converter circuit is associated with each one of the matrix vector multipliers, each having an input coupled to one of the summing bit lines, and a pulse output coupled to a different second one of the interconnect conductors of the user-programmable routing network.

Abstract: In some examples, a device includes shuffling circuitry configured to receive an input unary bit stream and generate a shuffled bit stream by selecting n-tuple combinations of bits of the input unary bit stream. The device also includes stochastic logic circuitry having a plurality of stochastic computational units configured to perform operations on the shuffled bit stream in parallel to produce an output unary bit stream, each of the stochastic computational units operating on a different one of the n-tuple combinations of the bits.

Abstract: Processing cores with data associative adaptive rounding and associated methods are disclosed herein. One disclosed processing core comprises an arithmetic logic unit cluster configured to generate a value for a unit of directed graph data using input directed graph data, a comparator coupled to a threshold register and a data register, a core controller configured to load a threshold value into the threshold register when the value for the unit of directed graph data is loaded into the data register, and a rounding circuit. The rounding circuit is configured to receive the value for the unit of directed graph data from the arithmetic logic unit cluster and conditionally round the value for the unit of directed graph data based on a comparator output from the comparator.

Abstract: According to one embodiment, a calculating device includes a processor repeating a processing procedure. The processing procedure includes a first variable update and a second variable update. The first variable update includes updating a first variable xi by adding a first function to the first variable xi before the first variable update. The second variable update includes updating the second variable yi by adding a second function and a third function to the second variable yi before the second variable update. A variable of the first function set includes a calculation parameter. The calculation parameter is different before and after the processing procedure. The processor performs at least an output of at least one of the first variable xi obtained after the repeating of the processing procedure or a function of the first variable xi obtained after the repeating of the processing procedure.

Abstract: Adder trees may be constructed for efficient packing of arithmetic operators into an integrated circuit. The operands of the trees may be truncated to pack an integer number of nodes per logic array block. As a result, arithmetic operations may pack more efficiently onto the integrated circuit while providing increased precision and performance.

Abstract: A random number generator, RNG, a method of fabricating the same, and a method of generating a random number. The RNG, comprises at least one first avalanche photodiode, APD, configured for producing “1” events based on dark electron initiated avalanches in the first APD; at least one second avalanche photodiode, APD, configured for producing “0” events based on dark electron initiated avalanches in the second APD; and a feedback circuit configured for substantially evening out the respective numbers of generated avalanches in the first and second APDs by independently controlling respective dynamic bias voltages of the first and second APDs.

Abstract: This disclosure describes techniques for processing data bits using pseudo-random deterministic bit-streams. In some examples, a device includes a pseudo-random bit-stream generator configured to generate bit combinations encoding first and second numerical values based on a proportion of the data bits in the sequence that are high relative to the total data bits in the sequence. The device also includes a stochastic computational unit configured to perform a computational operation on the bit combinations and produce an output bit-stream having a set of data bits indicating a result of the computational operation, wherein the data bits of the output bit-stream represent the result based on a probability that any data bit in the set of data bits of the output bit-stream is high.