Abstract: A mechanism is provided for run-time task-level dynamic energy management. An instruction address for a first instruction of the application is mapped to a portion of application code in the application in response to an application being marked for energy management. A monitoring of the hardware resource activities is done for the portion of the application code. A level of energy management is then implemented for the portion of the application code based on a value of the tick indicator, resource activities, and an intensity indicator.

Abstract: An interfacing device is configured to process one or more rules, based on sensor data, to perform a predetermined action. During operation, the device can receive a device configuration that includes a rule for the interfacing device. The rule can include an action description for performing an action, and can include a condition that takes sensor data as input and indicates criteria for performing the action. The device can store the rule in a rule repository, and determines a remote interfacing device that generates data associated with the rule's condition. The device can also subscribe to the data from the remote interfacing device.

Abstract: A monitoring system including a first and a second portion. The first portion includes a controller for receiving a code sequence. The first portion is configured to connect the system to a common data bus. The first portion is configured to provide a synchronization signal to the second portion when the two portions are in a predetermined position. The second portion includes a controller for providing the code sequence to the first portion and the first portion being further configured to output the code sequence for verification by a verification entity.

Abstract: One or more embodiments include an outlet interface that is configured to mate with an electrical outlet. The outlet interface is provided as an integral structure of the housing.

Abstract: A method and system for managing computational workload in a computerized system powered by an energy source. This invention relies first and foremost on adapting computational workload at the computerized system according to a time-varying property of the power supplied by the energy source, such that power generated at the source is optimized. A feedback mechanism is accordingly implemented which changes power available for computation, e.g., to track a more efficient energy generation efficiency point at the source.

Abstract: A laptop PC is enabled to operate with small power consumption while maintaining a specific function. A laptop PC is provided with a HDD and can operate in a normal mode and a doze mode as a new operating mode. In the doze mode, the computer can operate with power consumption less than in the normal mode while executing a process to implement a specific function. In the doze mode a shift event is created, and a process existing at that time is force-suspended or an I/O processing completion notification is suspended to a process that makes an I/O request to the HDD. As a result, the laptop PC is enabled to operate with small power consumption by stopping the HDD while maintaining a specific function.

Abstract: An application may receive a request to control a power mode. The power mode may be controlled based on the request and the operational status of the application. In one example, the power mode may be disabled until termination of the application. In another example, the power mode may be disabled for a specified amount of time or according to operational status of multiple applications and/or electronic pages. In yet another example, the power mode may be controlled according to an operating system power management configuration.

Abstract: Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data structure. The posting logic is to post the interrupt request in a data structure specified by information in the first data structure.

Abstract: Charging a device using a plurality of handshakes. A first device may provide a first handshake to a second device. A device of a first device type may be configured to charge its battery without further communication based on the first handshake. The first device may monitor a connection to the second device for a second handshake corresponding to a device of a second device type. In response to detecting the second handshake, the first device may provide a response to the second device. Accordingly, the second device of the second device type may be configured to charge its battery based on the second handshake.

Abstract: A memory includes a wordline driver having reduced leakage. The memory includes a storage array coupled to a first voltage supply, and a number of wordline driver units each including a driver inverter. During a low power mode, the voltage of the voltage supply coupled to the wordline circuit is reduced or removed, while the voltage of the voltage supply coupled to the storage array is kept at least at a retention voltage. In addition a p-type transistor is coupled between the array voltage supply and an input to the wordline driver inverter, thereby keeping the output of the wordline driver inverter at a low logic level to prevent inadvertent wordline firing.

Abstract: Embodiments of the present invention provide a traffic communication module and method of forming the same. Specifically, among other things, embodiments of the present invention provide a traffic communication module (e.g., also referred to herein as a C2V module) having a set of components for facilitating/enabling communication between a master device (e.g., a console) and a set of slave devices (e.g., validators) across multiple communication protocols (e.g., rs485, rs232c, UDP, etc.). In a typical embodiment, the C2V module comprises: an application programming interface (API) component for configuring the traffic communication module; a communication component coupled to the API component for facilitating communications between the master and slave devices based upon a set of communication protocols; and a communication type component for generating a set of protocol-specific data packet files for the communications.

Abstract: In some embodiments, a system can be configured to communicate to and from a media device. The media device can include a first controller. The system can include: (a) a software module configured to run on the first controller; (b) a physical device module configured to run on the first controller; (c) a virtual host module configured to run on the first controller; and (e) a docking station having: (1) a second controller; (2) an electrical connector configured to couple to the media device; (3) a physical host module configured to run on the second controller; (4) a virtual device module configured to run on the second controller; and (5) one or more accessory devices configured to communicate with the media device using the virtual device module. In some examples, the physical host module and the physical device module are configured to establish a physical communications pipe between the media device and the docking station.

Abstract: Metrics representing a combined measure of power used by a central processing unit (CPU) and power used by a graphics processing unit (GPU) are compared to a shared supply power and/or shared thermal power budget. A state of the CPU and a state of the GPU are regulated by the power management system to maintain the metrics within the shared supply power and/or thermal power budget for the purpose of managing the components to meet platform power supply, and cooling, constraints and design requirements.

Abstract: According to one exemplary embodiment, a host/client system includes a host module, which includes a CPU coupled to a system bridge. The host/client system further includes at least one client having an integrated interface, where the integrated interface is coupled to the system bridge through a scalable serial bus. The system bridge and the integrated interface enable high bandwidth communication between the CPU and the at least one client through the scalable serial bus, thereby allowing control of bus width between the host module and the client.

Abstract: Handshaking circuits are provided in a communications cable and in a device operable to be mated with the communications cable. Before a device can utilize the power supply signal of such a communications channel, the two handshaking circuits must sufficiently identify one another over a power supply signal with a decreased voltage. The decreased voltage allows for a cable plug to be provided with a safe, protected power that cannot cause harm to a human. The decreased voltage also reduces the chance that a device can receive a primary power supply signal from the cable before the device sufficiently identifies itself. Accordingly, a laptop may be connected to a portable music player, but the voltage of the power supply signal provided by the laptop to the cable may be decreased on-cable until the handshaking circuit of the portable music player sufficiently performs a handshaking operation with a on-cable handshaking circuit.

Abstract: An apparatus including a plurality of internal devices that communicates concurrently with a controller by one of the MDIO protocol and the SPI protocol is disclosed. The controller of the invention couples with respective devices by the point-to-point arrangement. The controller couples with the external apparatus by the MDIO protocol and receives a packet containing an address of one of internal devices, the controller communicates with the device defined by the address by the protocol attributed to the device.

Abstract: A system and method are described for warming a processor from a low power state in anticipation of a time critical interrupt. For example, one embodiment of a method comprises: detecting that a time-critical interrupt will require processor resources at some point in the future; estimating a time at which the time-critical interrupt will be triggered; scheduling a timer interrupt to fire at a specified time prior to the estimated time that the time-critical interrupt will be triggered, the timer interrupt being scheduled with sufficient time to ensure that the processor is warmed to a level at which it is capable of handling the time-critical interrupt at the time that the time-critical interrupt is triggered; and responsively triggering the timer interrupt at the specified time prior to the time critical interrupt.

Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.

Abstract: Methods, systems and devices configured to add synchronization to the entry and exit from low power modes in asynchronous operating systems on a multiprocessor system. A synchronizing agent tracks the requested sleep and wake up times of the different asynchronous operating systems executing on different cores of the same system on chip or multicore processor. The sleep/wake up times of some cores/operating systems may be delayed in order to synchronize the sleep/wake up times of two or more of the asynchronous operating systems executing on the multiprocessor system.