Abstract: An arbitration device includes an arbitration section, a counter, and a changing section. While write request signals and read request signals for a transfer path, are inputted from request sources, the arbitration section arbitrates an order that the write and read request signals use the transfer path, and when arbitration is settled, outputs use permission signals to the request sources. The changing section changes a time from outputting of the write request signals until inputting of the write request signals to the arbitration section, and/or a time from outputting of the use permission signals for the write request signals until inputting of the use permission signals to the request sources.

Abstract: A host device and a storage device with a Serial ATA (SATA) architecture to independently transition to a deeper low power state after first entering an initial low power state without first transitioning to the Active state. The transition from the Partial state to the Slumber state is direct and the transition may be enabled, but not negotiated through a handshaking process.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

Abstract: A system for controlling power usage in a storage cluster by dynamically controlling membership in the storage cluster is disclosed. The storage cluster includes multiple storage servers that provide access to one or more storage subsystems. The power management system uses a power management policy to set parameters for controlling membership in the storage cluster and monitors the storage cluster based on the policy. Based on the monitoring, the system detects when the number of storage servers in the storage cluster should be reduced or increased. To reduce the number, the system selects a storage server to deactivate and directs the selected storage server to migrate storage resources (e.g. data, metadata) associated with the server to a different storage server. The system then deactivates the selected storage server by directing it to transition to a low power mode. The system may increase the number of servers in the storage cluster by reversing these steps.

Abstract: A system and method for information preservation on a portable electronic device is disclosed. A signal indicating an energy capacity threshold remaining in the battery of a hand held device may be generated. Then, responsive to such a signal, information may be copied from a volatile memory into a non-volatile memory. The non-volatile memory may be configured to provide instructions for direct execution by a processor, or the non-volatile storage may be attached via an expansion interface. The non-volatile memory may be a removable card. The copy function is typically done in low power modes. Alternatively, the information is only copied provided sufficient battery capacity remains to perform the copy function.

Abstract: Embodiments of a method and system for conserving power used in a central processing unit (CPU) are described. An embodiment uses direct memory access (DMA) fetch suspend logic to allow the CPU to stay in a sleep state indefinitely until a break event occurs. Embodiments include power management monitoring and Universal Serial Bus (USB) descriptor monitoring logic. Power management monitor logic monitors the CPU sleep state and sets a status flag to the USB descriptor monitoring logic whenever the CPU is in a predefined sleep state. The USB descriptor monitoring logic monitors the fetching of linked descriptor lists. When the CPU status flag is raised, it causes monitoring of the descriptor fetch by the USB descriptor monitoring logic. If the USB controller has completed all of the descriptor fetches while the CPU sleep flag is true, this logic sets a flag to cause the USB controller to suspend DMA fetch operations.

Abstract: A method and system for hotplug removing a device in a virtual machine system. A computer system hosts a virtual machine that runs a guest. A hotplug manager in the computer system sends a request to the guest for hotplug removal of a device associated with the guest. The hotplug manager detects an indication of reboot of the guest, and completes the hotplug removal in response to detection of the reboot.

Abstract: An information processing device, such as cellular phone, includes a first timer set for executing count processing applied to a preassigned first processing, a second timer set for executing count processing applied to the preassigned first processing, a display state determination unit configured to determine a display state of a display unit, and a timer switching unit configured to select and set the first timer for the preassigned first processing at a time when the display state determination unit determines that the display unit is in an “ON” state and to select and set the second timer for the preassigned first processing at a time when the display state determination unit determines that the display unit is in an “OFF” state.

Abstract: A method of communicating data between an external storage device and a USB host via a USB device is disclosed. The method includes receiving data from the USB host; and either (1) directly communicating the received data to the external storage device via an exclusive bus, or (2) indirectly communicating the received data to the external storage device via a USB bus, separate from the exclusive bus.

Abstract: A network system that is part of a main system includes: a first PCI express-network bridge with a first control unit and a first PCI express adapter terminating a first PCI express bus; and a second PCI express-network bridge connected to the first PCI express-network bridge through a network. The second PCI express-network bridge includes a second control unit and a second PCI express adapter terminating a second PCI express bus, wherein the first control unit detects a destination of a packet sent from the first PCI express adapter, searches a physical address of the destination from a packet encapsulating table, and encapsulates the packet in a frame so that the frame includes the physical address, and wherein the second control unit removes the encapsulation tagged to the packet, and transfers the packet to the destination through the second PCI express bus by referring to a PCI express configuration register.

Abstract: A processing system includes a shared resource, an arbitration module, and a requesting device for issuing requests to the arbitration module to access the shared resource to perform transactions on the shared resource. The arbitration module grants access to the requesting device for a fixed time duration. The fixed time duration comprises one of a plurality of time durations including a first and a second time duration; the second longer than the first. The requesting device prioritizes performance of the transactions on the shared resource based upon the fixed time duration and types of transactions to be performed. Transaction type comprises one of a plurality of types including a first type that requires a time duration that can be performed within the first time duration and a second type that requires a time duration that exceeds the first time duration but can be performed within the second time duration.

Abstract: A switch system has a master sub-switch and a slave sub-switch, the master sub-switch having a first bridge for transmitting the received packet via the first bus, a second bridge for transmitting the packet when the address information of the second bridge matches with the address information included in the packet, and a third bridge for receiving the packet from the first bridge and transmitting the packet to the slave sub-switch, the slave sub-switch having a fourth bridge for receiving the packet from the third bridge and transmitting the packet, and a fifth bridge for receiving the packet from the fourth bridge, and transmitting the packet when the address information of the fifth bridge matches with the address information included in the packet, wherein the master sub-switch has a table including address information of the fifth bridge, and transmits the packet to the fifth bridge in reference to the table.

Abstract: Power supply of ECUs connected to a communication network is optimally controlled so that power consumption is reduced. A transceiver/receiver converts a message of a differential signal received via a CAN bus into a digital signal. A select circuit determines whether the converted message is in a CAN format or a UART format. If it is in the UART format, the select circuit outputs a message to the UART circuit. A UART circuit determines whether the message matches a UART format. If matched, an ID determination circuit determines whether the input message is specifying a CAN ID of its own ECU. If it is the CAN ID of the ECU, the ID determination circuit outputs an enable signal to turn on a regulator and supply power to an MCU and an actuator.

Abstract: Managing concurrent serialized interrupt broadcast commands in a multi-node, symmetric multiprocessing computer including receiving, by a communications adapter in a compute node, a plurality of serialized interrupt broadcast commands; receiving, by the communications adapter, a plurality of interrupt tags for the plurality of serialized interrupt broadcast commands, each interrupt tag including an identification of an interrupt service order for a serialized interrupt broadcast command; assigning, by the communications adapter, to each serialized interrupt broadcast command its interrupt tag; and if an interrupt tag assigned to a serialized interrupt broadcast command has an interrupt service order that matches a value of a current operation tag that identifies the next serialized interrupt broadcast command to be exposed to the one or more processors, exposing, by the communications adapter, the serialized interrupt broadcast command to the one or more processors on the compute node to be serviced.

Abstract: Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.

Abstract: A digital image system which transmits digital image data, and more particularly, to a digital image system in a high definition multimedia interface (HDMI) format or a digital visual interface (DVI) format.

Abstract: A time aligning circuit includes a plurality of buffers, a plurality of delay selectors, a plurality of adjustment symbol generators, and a controller. Each buffer receives an ordered set on a corresponding lane. Each delay selector delays an output of the ordered set of the corresponding buffer. Each adjustment symbol generator outputs an adjustment symbol or the output received from the corresponding delay selector according to an adjustment control signal. When an initial symbol of a designated delay selector is detected but initial symbols of other delay selectors are not received yet, the controller generates the delay control signal to the designated delay selector and generates the adjustment control signal to control a designated adjustment symbol generator corresponding to the designated delay selector in order to output one adjustment symbol until initial signals of all delay selectors are detected.

Abstract: A certain ECU transmits a reference message for requiring the other ECUs to transmit data. After transmission of the reference message, each of all the ECUs transmits priority information of its transmit message onto a communication bus, and then detects whether some priority information transmitted from the other ECUs has a higher priority than its own transmitted priority information. If there is detected no priority information of a higher priority than its own transmitted priority information, it transmits a message associated therewith, and then is prohibited to transmit data of the same priority until receiving a next reference message.

Abstract: A modification method and system. The method includes detecting and monitoring by a computing system, a frequency signal associated with an input voltage signal used for powering a plurality of power consumption devices at a specified location. The computing system compares the frequency signal to a predetermined frequency value. The computing system determines that the frequency signal comprises a first value that is not equal to the predetermined frequency value. The computing system calculates a difference value between the first value and the predetermined frequency value. The computing system compares the difference value to a second value. The computing system enables a load adjustment modification process associated with the plurality of power consumption devices. The computing system generates and stores a report associated with the load adjustment modification process.

Abstract: An area efficient system that includes a first circuit to synchronize a clock signal and a data signal and a data retaining and processing device to receive data from said data bus to thereby generate a status signal indicating the receipt of data by said area efficient system; a reference bus address and said data bus. The system also includes a device to compare the reference bus address with the content of memory for generating an address matching signal and a control signal generator to govern the data write signal generation for said shifting means. The system further includes a sequencer to read and write data from/to said data retaining and processing device in a plurality of subcycles for efficiently accessing storage buffers and a direct storage access controlling means for generating interrupt signals and access request signals.