Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a first redistribution structure, a second redistribution structure, a first semiconductor die, a second semiconductor die and an encapsulant. The second redistribution structure is vertically overlapped with the first redistribution structure. The first and second semiconductor dies are located between the first and second redistribution structures, and respectively have an active side and a back side opposite to the active side, as well as a conductive pillar at the active side. The back side of the first semiconductor die is attached to the back side of the second semiconductor die. The conductive pillar of the first semiconductor die is attached to the first redistribution structure, whereas the conductive pillar of the second semiconductor die extends to the second redistribution structure.

Abstract: Disclosed is an electronic circuit. The electronic circuit includes a first transistor device and a clamping circuit. The first transistor device includes a control node and a load path between a first load node and a second load node, and the clamping circuit includes a second transistor device and a drive circuit. The second transistor device includes a control node and a load path connected in parallel with the load path of the first transistor device, and the drive circuit includes a capacitor coupled between the second load node of the first transistor device, and a first resistor coupled between the control node of the second transistor device and a further circuit node.

Abstract: Disclosed is a display device with high resolution. The display device includes a substrate, a plurality of signal lines on the substrate, multiple buffer layers including at least one organic buffer layer and at least one inorganic buffer layer, and at least one transistor that overlaps one or more of the plurality of signal lines, with the multiple buffer layers interposed therebetween. Accordingly, it may be possible to ensure a sufficient process margin and consequently to realize a high resolution and improve production yield.

Abstract: An apparatus comprising a chemical field effect transistor array in a circuit-supporting substrate is disclosed. The transistor array has disposed on its surface an array of sample-retaining regions capable of retaining a chemical or biological sample from a sample fluid. The transistor array has a pitch of 10 ?m or less and a sample-retaining region is positioned on at least one chemical field effect transistor which is configured to generate at least one output signal related to a characteristic of a chemical or biological sample in such sample-retaining region.

Abstract: A semiconductor device of the present invention includes a semiconductor layer including a main IGBT cell and a sense IGBT cell connected in parallel to each other, a first resistance portion having a first resistance value formed using a gate wiring portion of the sense IGBT cell and a second resistance portion having a second resistance value higher than the first resistance value, a gate wiring electrically connected through mutually different channels to the first resistance portion and the second resistance portion, a first diode provided between the gate wiring and the first resistance portion, a second diode provided between the gate wiring and the second resistance portion in a manner oriented reversely to the first diode, an emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the main IGBT cell, and a sense emitter electrode disposed on the semiconductor layer, electrically connected to an emitter of the sense IGBT cell.

Abstract: A package structure includes a first encapsulation member, a second encapsulation member, at least one semiconductor chip, a plurality of metal pins and a second insulation layer. The first encapsulation member includes a first metal layer, a first insulation layer and a second metal layer. The at least one semiconductor chip is disposed between the first encapsulation member and the second encapsulation member. The at least one semiconductor chip comprises a plurality of conductive terminals connected with the first metal layer or a third metal layer. The plurality of metal pins are disposed between and extended outward from the first encapsulation member and the second encapsulation member. The second insulation layer is disposed between the first encapsulation member and the second encapsulation layer for securing the first encapsulation member, the second encapsulation member, the at least one semiconductor chip, and the plurality of metal pins.

Abstract: An electronic device for monitoring an electrical quantity out of a voltage and arc intensity relative to an alternating current flowing in an electrical conductor, includes a measurement module configured to measure at least one value of the electrical quantity, a wireless transceiver, and a transmission module linked to the wireless transceiver. The monitoring device furthermore includes a computation module configured to compute at least one parameter for monitoring the electrical quantity as a function of at least one measured value of the electrical quantity, each monitoring parameter being chosen from an angular phase of the electrical quantity and a modulus of the electrical quantity, the transmission module being configured to transmit, to another electronic device, a data message containing at least one computed monitoring parameter.

Abstract: A transistor device is disclosed. The transistor device includes: a semiconductor body; a source conductor on top of the semiconductor body; a source clip on top of the source conductor and electrically connected to the source conductor; a first active device region arranged in the semiconductor body, covered by the source conductor and the source clip, and including at least one device cell; and a second active device region arranged in the semiconductor body, covered by regions of the source conductor that are not covered by the source clip, and including at least one device cell. The first active device region has a first area specific on-resistance and the second active device region has a second area specific on-resistance, the second area specific on-resistance being greater than the first area specific on-resistance.

Abstract: An organic light-emitting display apparatus including a substrate having a display area and a peripheral area; a TFT in the display area; an organic insulating layer on the TFT; an OLED that includes a pixel electrode electrically connected to the TFT, an emission layer on the pixel electrode, and a counter electrode facing the pixel electrode with the emission layer therebetween; a pixel-defining layer on the organic insulating layer and having an opening overlying the pixel electrode; a first dam in the peripheral area; a second dam in the peripheral area to surround an outer periphery of the first dam; a metal-containing layer covering the first dam and including a same material as the pixel electrode; and a thin-film encapsulator on the substrate to cover the OLED and including a first and second inorganic films, and an organic film between the first and second inorganic films.

Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device includes a plurality of dies, a logic die coupled to the plurality of dies, and a dummy die thereon. In selected examples, the dummy die is located between the logic die and the plurality of silicon dies. In selected examples, the dummy die is attached to the logic die.

Abstract: A semiconductor device includes a semiconductor film, a semiconductor auxiliary film, a wiring line, a first metal film, and an interlayer insulating film. The semiconductor film includes a channel region and a low-resistance region. The semiconductor film includes indium and oxygen. The semiconductor auxiliary film is in contact with the low-resistance region of the semiconductor film and reduces the electric resistance of the semiconductor film. The wiring line is electrically coupled to the low-resistance region of the semiconductor film. The first metal film covers the wiring line and has a higher standard electrode potential than the indium. The interlayer insulating film covers the semiconductor film with the first metal film interposed therebetween. The interlayer insulating film has a first hole and a second hole. The first hole is provided at a position opposed to the low-resistance region of the semiconductor film. The second hole reaches the first metal film.

Abstract: Semiconductor devices and fabrication methods are provided. An exemplary fabrication method includes providing a semiconductor substrate; forming at least one gate structure having a gate dielectric layer on a surface of the semiconductor substrate; forming first sidewall spacers on a first sidewall surface region of the gate structure and covering sidewall surfaces of the gate dielectric layer; forming second sidewall spacers on a second sidewall surface region of the gate structure and top surfaces of the first sidewall spacers and made of a material different from a material of the first sidewall spacers; forming conductive plugs in the dielectric layer at both sides of the gate structure, the first sidewall spacers and the second sidewall spacers; and removing the second sidewall spacers to form air gap spacers above the first sidewall spacers and between the second sidewall surface region of the gate structure and the conductive plugs.

Abstract: A display substrate comprises a display area and a non-display area around the display area; at least one ground terminal located in the non-display area; a first wiring disposed in the non-display area and being around the display area; and a second wiring disposed between the first wiring and the display area and being positioned around the non-display area. The second wiring is provided with at least one tip on a side closer to the first wiring, the at least one tip pointing to the side of the first wiring. The first wiring and the second wiring are respectively connected to the at least one ground terminal.

Abstract: The present disclosure relates to the field of display technologies, and provides an OLED light emitting module, a manufacturing method thereof, and a display device. The OLED light emitting module includes a base substrate, an OLED light emitting device on the base substrate, and a metal stack on the OLED light emitting device. The metal stack includes a first metal layer, a second metal layer and a third metal layer arranged in stack. The second metal layer includes an invar alloy. The first metal layer and the third metal layer include a metal material different from the invar alloy.

Abstract: In some example embodiments, a back side illumination (BSI) image sensor may include a pixel configured to generate electrical signals in response to light incident on a back side of a substrate. In some example embodiments, the pixel includes, a photodiode, a device isolation film adjacent to the photodiode, a dark current suppression layer above the photodiode, a light shield grid above the photodiode and including an opening area of 1 to 15% of an area of the pixel, a light shielding filter layer above the light shield grid, a planarization layer above the light shielding filter layer, a lens above the planarization layer, and/or an anti-reflective film between the photodiode and the lens.

Abstract: An e-Fuse device including a first electronic feature and a second electronic feature comprised of a conductive material, each of the first electronic feature and the second electronic feature having a width at least as great as a ground rule of a patterning process; and a fuse element comprised of the conductive material having a width less than the ground rule of the patterning process, the fuse element connecting a bottom portion of the first electronic feature and a bottom portion of the second electronic feature. Also disclosed is a method of making the e-Fuse device.

Abstract: A semiconductor device includes a substrate; an insulating layer positioned above the substrate, wherein the insulating layer has two ends; a first doped region formed in the substrate and positioned at one end of the two ends of the insulating layer; a second doped region formed in the substrate and positioned at the other end of the two ends of the insulating layer, wherein the second doped region is opposite to the first doped region; a control terminal positioned above the insulating layer; a first fuse head positioned above the control terminal and electrically coupled to the first doped region; a second fuse head positioned above the first fuse head; and a fuse area positioned between the first fuse head and the second fuse head.

Abstract: A reconfigurable phase change device with methods for operating and forming the same are disclosed. An example device can comprise a reconfigurable layer comprising a phase change material, and a set of contacts connected with the reconfigurable layer. The set of contacts can comprise at least a first contact, a second contact, and a third contact. The device can comprise at least one control element electrically coupled with one or more of the set of contacts. The at least one control element can be configured to supply a first control signal to one or more of the set of contacts. The first control signal can be configured to modify a first portion of the reconfigurable layer thereby isolating the first contact from the second contact and the third contact.

Abstract: A component includes a light emitting semiconductor chip, wherein the semiconductor chip includes a layer arrangement including a plurality of layers, the p-conducting layer and the n-conducting layer adjoin one another in an active zone, a first electrical contact is configured on the p-conducting side of the layer arrangement at a first side of the semiconductor chip, a second electrical contact is configured on the n-conducting side of the layer arrangement at a second side of the semiconductor chip, the second side being situated opposite the first side of the semiconductor chip, the first side of the semiconductor chip transitions into the second side via an end side, the semiconductor chip is secured by the end side on a substrate, the substrate includes a first and second further electrical contact, and the further electrical contacts electrically conductively connect to the electrical contacts of the semiconductor chip.

Abstract: A semiconductor component has a gate structure that extends from a first surface into an SiC semiconductor body. A body area in the SiC semiconductor body adjoins a first side wall of the gate structure. A first shielding area and a second shielding area of the conductivity type of the body area have at least twice as high a level of doping as the body area. A diode area forms a Schottky contact with a load electrode between the first shielding area and the second shielding area.