Abstract: A metal layer structure is disclosed. The metal layer structure includes a substrate, a first dielectric layer on a surface of the substrate, and at least one first conductor and at least one second conductor on the first dielectric layer. The second conductor has at least one thin portion.

Abstract: It is an object of the present invention to provide a high reliable EL display device and a manufacturing method thereof by shielding intruding moisture or oxygen which is a factor of deteriorating the property of an EL element without enlarging the EL display device. In the invention, application is used as a method for forming a high thermostability planarizing film 16, typically, an interlayer insulating film (a film which serves as a base film of a light emitting element later) of a TFT in which a skeletal structure is configured by the combination of silicon (Si) and oxygen (O). After the formation, an edge portion or an opening portion is formed to have a tapered shape. Afterwards, distortion is given by adding an inert element with a comparatively large atomic radius to modify or highly densify a surface (including a side surface) for preventing the intrusion of moisture or oxygen.

Abstract: The invention concerns a photovoltaic device (1) comprising a plurality of p-i-n type photovoltaic cells (2) arranged on a substrate (3), wherein said cells (2) are arranged, in the form of a single layer, parallel to one another and the electrical conductive layer (7) is arranged between the n layer (6) and the p layer (5) of each consecutive cell (2) so as to electrically connect said cells (2) in series. The invention also concerns the use of such a device (1) as glazing, a method for making such a device (1), a method for controlling a transparent photovoltaic device (1) as well as an installation for implementing said control method.

Abstract: In order to improve the soft error resistance of a memory cell of an SRAM without increasing its chip size in deep through-holes formed by perforating a silicon oxide film, there is a silicon nitride film and a silicon oxide film, a capacitor element having a TIN film serving as a lower electrode. This capacitor element is connected between a storage node and a supply voltage line, between a storage node and a reference voltage line, or between storage nodes of the memory cell of the SRAM.

Abstract: A semiconductor photodetecting device is provided for enabling a solid-state image sensor to meet the requirements of higher quality imaging and more reduction in cost. The photodetecting device of the present invention includes: a semiconductor substrate; and an epitaxial layer formed on the semiconductor substrate by epitaxial growth. The epitaxial layer has a multilayer structure including: a first pn junction layer; a first insulating layer; a second pn junction layer; a second insulating layer; and a third pn junction layer. The first insulating layer and the second insulating layer have openings, and the first pn junction layer and the second pn junction layer are adjacent to each other through the openings of the first insulating layer which is placed in between these pn junction layers, and the second pn junction layer and the third pn junction layer are adjacent to each other through the openings of the second insulating layer which is placed in between these pn junction layers.

Abstract: A novel transistor structure and method for fabricating the same. The transistor structure comprises (a) a substrate and (b) a semiconductor region, a gate dielectric region, and a gate region on the substrate, wherein the gate dielectric region is sandwiched between the semiconductor region and the gate region, wherein the semiconductor region is electrically insulated from the gate region by the gate dielectric region, wherein the semiconductor region comprises a channel region and first and second source/drain regions, wherein the channel region is sandwiched between the first and second source/drain regions, wherein the first and second source/drain regions are aligned with the gate region, wherein the channel region and the gate dielectric region (i) share an interface surface which is essentially perpendicular to a top surface of the substrate, and (ii) do not share any interface surface that is essentially parallel to a top surface of the substrate.

Abstract: The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

Abstract: A semiconductor device includes: an insulating tape having a device hole and a plurality of holes; a plurality of leads formed on one surface of the tape and extending at one end into the device hole and at the other end into the holes; a semiconductor chip having a plurality of electrodes on a main surface thereof, being connected with the leads extending into the device hole; an encapsulant formed of an insulating resin, the leads and a predetermined portion of the tape; bump electrodes provided on one surface of the leads; slits provided in the tape between the encapsulant and the bump electrodes and extending along a column of the bump electrodes; and a warp prevention reinforcement made of an insulating film and formed over the tape; wherein the semiconductor chip and the bump electrodes are connected to one and the same surface side of the leads.

Abstract: An integrated semiconductor circuit includes a transistor and a strip conductor (11). The transistor includes a first (1) and a second source/drain region (2) and a gate electrode. The strip conductor (11) is electrically insulated from a semiconductor body at least by a gate dielectric and forms the gate electrode in the area of the transistor. The strip conductor (11) extends along a first direction (x) in the area of the transistor. The second source/drain region (2) is arranged offset with respect to the first source/drain region (1) in the first direction (x). The transistor thus formed has an inversion channel (K1) that only extends between two corner areas (1a, 2a) facing one another of the first and of the second source/drain region, i.e. is much narrower than in the case of a conventional transistor.

Abstract: A protective barrier layer, formed of a material such as titanium or titanium nitride for which removal by chemical mechanical polishing (CMP) is primarily mechanical rather than primarily chemical, formed on a conformal tungsten layer. During subsequent CMP to pattern the tungsten layer, upper topological regions of the protective barrier layer (such as those overlying interlevel dielectric regions) are removed first, exposing the tungsten under those regions to removal, while protective barrier layer regions over lower topological regions (such as openings within the interlevel dielectric) remain to prevent chemical attack of underlying tungsten. CMP patterned tungsten is thus substantially planar with the interlevel dielectric without dishing, even in large area tungsten structures such as MOS capacitor structures.

Abstract: A first semiconductor element is mounted on a base plate, and is in a sealed state by the periphery thereof being covered by an insulation member, and the upper surface thereof being covered by an upper insulation film. An upper wiring layer formed on the upper insulation film, and the lower wiring layer formed below the base plate via lower insulation films are connected by conductors. A second semiconductor element is mounted exposed, being connected to the lower wiring layer.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, a lightly-doped semiconductor layer of the first conductivity type formed on the first major surface of the substrate, a first semiconductor region of the first conductivity type formed on an island-shaped region on the lightly-doped semiconductor layer, a first electrode surrounding the first semiconductor region and buried at a deeper position than the first semiconductor region, a second semiconductor region formed on the second major surface of the substrate, a buried field relaxation layer formed in the lightly-doped semiconductor layer between a bottom surface of the first electrode and the second semiconductor region, including a first field relaxation layer of the first conductivity type and second field relaxation layers of the second conductivity type formed at two ends of the first field relaxation layer, second and third electrodes formed on the first and second semiconductor regions, respectively.

Abstract: A photodetector device is provided which comprises a photodiode for generating an electrical signal corresponding to an amount of incident light, and a logarithmic conversion transistor for subjecting a voltage value of the electrical signal to logarithmic conversion. The logarithmic conversion transistor comprises a first electrode which is one of a source electrode and a drain electrode, a second electrode which is the other of the source electrode and the drain electrode, and a gate electrode. The first electrode is connected to the photodiode. A first voltage is applied to the second electrode so that the logarithmic conversion transistor operates in a subthreshold region. The photodetector device further comprising a section for causing a voltage of the gate electrode to be in a floating state when the logarithmic conversion transistor subjects the voltage value of the electrical signal to logarithmic conversion.

Abstract: An apparatus for depositing a thin film on a substrate and product produced thereby are disclosed. In particular, deposition of the thin film is carried out on the substrate having an applied pressure. This applied pressure flexes the substrate to reduce in-plane stresses, wherein removal of the applied pressure after deposition of the thin film modifies the in-film stress for the thin film. With the above-described arrangement, it is possible to minimize the deterioration of electric characteristics of a semiconductor device and the occurrence of defects, such as film delamination, substrate cracks, and the like.

Abstract: The invention relates to a vertical transistor and an oxidation process that achieves a substantially curvilinear recess bottom. The recess serves as the gate receptacle that may facilitate a more uniform gate oxide layer. One embodiment relates to a storage cell that is disposed in the recess along with an electrode. Another embodiment relates to a system that includes the vertical transistor or the vertical storage cell.

Abstract: The semiconductor device comprises a copper interconnection 26b buried in an insulating film 16, and a dummy pattern for chemical mechanical polishing buried in the insulating film 16 near the copper interconnection 26b. The unit patterns 26c of the dummy pattern are formed in the density of 10-25%. Even in the case that the electrolytic plating solution for bottom up growth mechanism is used, the step on the surface of a copper film due to over-plating can be decreased, and the total plating thickness necessary to fill the interconnection trenches can be decreased.

Abstract: A semiconductor memory device may comprise a thyristor-based memory having some portions formed in strained silicon, and other portions formed in relaxed silicon. In a further embodiment, a thyristor in the thyristor-based memory may be formed in a region of relaxed silicon germanium, while an access device to the thyristor-based memory may have a body region incorporating a portion of a layer of strained silicon. In yet a further embodiment, different regions of the thyristor may be formed in vertical aligned relationship relative to an upper surface of the relaxed silicon germanium. For this embodiment, the thyristor may be formed substantially within the depth of the relaxed silicon germanium layer. In a method of forming the semiconductor device, relaxed silicon may be deposited over exposed regions of a silicon substrate, and a thin layer of strained silicon formed over a portion of the substrate having silicon germanium.

Abstract: The present invention relates to metal-insulator-metal (MIM) capacitors and field effect transistors (FETs) formed on a semiconductor substrate. The FETs are formed in Front End of Line (FEOL) levels below the MIM capacitors which are formed in upper Back End of Line (BEOL) levels. An insulator layer is selectively formed to encapsulate at least a top plate of the MIM capacitor to protect the MIM capacitor from damage due to process steps such as, for example, reactive ion etching. By selective formation of the insulator layer on the MIM capacitor, openings in the inter-level dielectric layers are provided so that hydrogen and/or deuterium diffusion to the FETs can occur.

Abstract: In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

Abstract: A recess gate-type semiconductor device includes a gate electrode having a recessed portion at least partially covering a recess trench in an active region, and source/drain regions disposed in the active region that are separated by the gate electrode. The recess trench is separated from sidewalls of a device isolation region in a first direction and contacts sidewalls of the device isolation region in a second direction. The width of the recess trench of the active region in the second direction may be greater than the width of the source/drain regions in the second direction, and the recessed portion of the gate electrode may have tabs protruding in the first direction at its corners. Therefore, the semiconductor device has excellent junction leakage current and excellent refresh characteristics.