Patents Examined by Matthew E. Warren
  • Patent number: 11916127
    Abstract: Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi Yang Wei, Bi-Shen Lee, Hsin-Yu Lai, Hai-Dang Trinh, Hsing-Lien Lin, Hsun-Chung Kuang
  • Patent number: 11910614
    Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: February 20, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang Sup Lee, Phil Ouk Nam, Sung Yun Lee, Chang Seok Kang
  • Patent number: 11910616
    Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.
    Type: Grant
    Filed: August 9, 2022
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 11903217
    Abstract: An integrated chip including a semiconductor layer over a substrate. A pair of source/drains are arranged along the semiconductor layer. A first metal layer is over the substrate. A second metal layer is over the first metal layer. A ferroelectric layer is over the second metal layer. The first metal layer has a first crystal orientation and the second metal layer has a second crystal orientation different from the first crystal orientation.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: February 13, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Chieh Huang, Hai-Ching Chen, Chung-Te Lin
  • Patent number: 11895894
    Abstract: A display apparatus includes a display panel including a plurality of pixels, and a cover panel including a window layer, an optical filter layer, a color filter layer and a bezel layer. The window layer includes a transmission region and a bezel region adjacent to the transmission region. The optical filter layer is disposed on the transmission region of the rear surface of the window layer. The color filter layer is disposed on the optical filter layer and includes a quantum dot. The bezel layer is disposed on the bezel region of the rear surface. The optical filter layer includes a partition wall layer, in which an opening is defined, a light-blocking layer disposed on the partition wall layer, and a reflection layer disposed in the opening. The bezel layer has a same color as the light-blocking layer.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: February 6, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jeongki Kim, Jang-Il Kim, Jeaheon Ahn, YeoGeon Yoon, Seok-Joon Hong
  • Patent number: 11889723
    Abstract: A display device including a substrate that includes a circuit layer; an insulating layer on the substrate; a pixel defining layer on the insulating layer, the pixel defining layer having an opening exposing a region of a top surface of the insulating layer; a light blocking layer covering a top surface and a side surface of the pixel defining layer; and an organic electroluminescent element in the opening, wherein the organic electroluminescent element includes a first electrode on the region of the top surface of the insulating layer exposed through the opening; at least one organic layer on the first electrode; and a second electrode on the at least one organic layer.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: January 30, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byung-chul Kim, Sujeong Kim, Kiyoung Yeon, Sun-kyu Joo, Chul Huh, Inok Kim, Hyeran Mun, Inseok Song, Wooyoung Lee, Yui-ku Lee
  • Patent number: 11876152
    Abstract: An electronic component mounting package includes: a substrate with ceramic as a base material, the substrate including a cavity having a bottom surface where an electronic component mounting part is located and an inner periphery that has a corner part and a straight part; and an inner peripheral surface where a first metal film is located, the first metal film having a thickness larger at the straight part than at the corner part on the inner periphery having a single distance from the bottom surface or the first metal film having a surface roughness larger at the straight part than at the corner part on the inner periphery having a single distance from the bottom surface.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: January 16, 2024
    Inventors: Akihiko Kitagawa, Yoshiaki Itakura
  • Patent number: 11869989
    Abstract: An electrode structure includes: a metal film with an opening formed in a part of the metal film; and a transparent conductive film disposed in the opening, wherein the transparent conductive film is electronically connected to an element and overlaps with the element as viewed in a plan view in a thickness direction of the transparent conductive film.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: January 9, 2024
    Assignee: TDK CORPORATION
    Inventors: Tomohito Mizuno, Takekazu Yamane, Hideaki Fukuzawa, Tetsuya Shibata
  • Patent number: 11871579
    Abstract: A semiconductor memory device of an embodiment includes: a semiconductor layer extending in a first direction; a first gate electrode layer; a second gate electrode layer provided apart from the first gate electrode layer in the first direction; and a gate insulating layer containing oxygen and at least one metal element of hafnium or zirconium, the gate insulating layer including a first region between the first gate electrode layer and the semiconductor layer, a second region between the first gate electrode layer and the second gate electrode layer, and a third region between the second gate electrode layer and the semiconductor layer, the first region including a crystal of an orthorhombic crystal system or a trigonal crystal system as a main constituent substance, and a distance between the second region and the semiconductor layer being larger than a distance between the first region and the semiconductor layer.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: January 9, 2024
    Assignee: Kioxia Corporation
    Inventors: Kunifumi Suzuki, Yuuichi Kamimuta
  • Patent number: 11856783
    Abstract: A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures have respective different thicknesses in accordance with the varying width of the first and second conductive structures.
    Type: Grant
    Filed: August 26, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Peng-Chun Liou, Ya-Yun Cheng, Yi-Ching Liu, Meng-Han Lin, Chia-En Huang
  • Patent number: 11855204
    Abstract: Provided is a memory device. The memory device includes: a substrate; a gate insulating film disposed on the substrate; a ferroelectric thin film disposed on the gate insulating film; a blocking film disposed on the ferroelectric thin film; and a gate pattern disposed on the blocking film, wherein the ferroelectric thin film includes a spacer having a fixed polarization regardless of an electric field that is applied from an outside, and a ferroelectric domain having a polarization controlled by the electric field that is applied from the outside, and a plurality of spacers and a plurality of ferroelectric domains are alternately and repeatedly provided in a direction parallel to a top surface of the substrate (in a b-lattice direction).
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: December 26, 2023
    Assignee: UNIST (Ulsan National Institute of Science and Technology)
    Inventors: Jun Hee Lee, Hyun Jae Lee, Chang Hoon Kim
  • Patent number: 11856781
    Abstract: A method of forming a three-dimensional (3D) memory device includes: forming, over a substrate, a layer stack having alternating layers of a first conductive material and a first dielectric material; forming trenches extending vertically through the layer stack from an upper surface of the layer stack distal from the substrate to a lower surface of the layer stack facing the substrate; lining sidewalls and bottoms of the trenches with a memory film; forming a channel material over the memory film, the channel material including an amorphous material; filling the trenches with a second dielectric material after forming the channel material; forming memory cell isolation regions in the second dielectric material; forming source lines (SLs) and bit lines (BLs) that extend vertically in the second dielectric material on opposing sides of the memory cell isolation regions; and crystallizing first portions of the channel material after forming the SLs and BLs.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: TsuChing Yang, Hung-Chang Sun, Kuo Chang Chiang, Sheng-Chih Lai, Yu-Wei Jiang
  • Patent number: 11855047
    Abstract: A chip package structure is provided. The chip package structure includes a chip structure. The chip package structure includes a first ground bump below the chip structure. The chip package structure includes a conductive shielding film disposed over the chip structure and extending onto the first ground bump. The conductive shielding film has a curved bottom surface.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, An-Jhih Su, Jing-Cheng Lin, Po-Hao Tsai
  • Patent number: 11856782
    Abstract: 3D memory array devices and methods of manufacturing are described herein. A method includes etching a first trench and a second trench in a multilayer stack, the multilayer stack including alternating dielectric layers and sacrificial layers. The method further includes forming a word line by replacing a sacrificial layer with a conductive material. Once the word line has been formed, a first transistor is formed in the first trench, the first transistor including a first channel isolation structure. A cut channel plug is formed in the second trench, a centerline of the cut channel plug being aligned with a centerline of the channel isolation structure. The method further includes forming a second transistor in the second trench adjacent the cut channel plug, the word line being electrically coupled to the first transistor and the second transistor.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yu Ling, Katherine H. Chiang, Chung-Te Lin
  • Patent number: 11849572
    Abstract: Embodiments disclosed herein include three-dimensional 3D arrays of memory cells and methods of forming such devices. In an embodiment a memory device comprises, a substrate surface, and a three-dimensional (3D) array of memory cells over the substrate surface. In an embodiment each memory cell comprises a transistor and a capacitor. In an embodiment the transistor of each memory cell comprises, a semiconductor channel, with a first end of the semiconductor channel electrically coupled to a bit line that runs substantially parallel to the substrate surface, and a second end of the semiconductor channel is electrically coupled to the capacitor. The transistor may also comprise a gate dielectric on a surface of the semiconductor channel between the first end and the second end of the semiconductor channel. In an embodiment, the gate dielectric is contacted by a word line that runs substantially perpendicular to the substrate surface.
    Type: Grant
    Filed: January 14, 2019
    Date of Patent: December 19, 2023
    Assignee: Intel Corporation
    Inventors: Aaron Lilak, Sean T. Ma, Abhishek Sharma
  • Patent number: 11844224
    Abstract: A method of forming a memory structure includes the following steps. A CMOS circuitry is formed over a semiconductor substrate. A bit line array is formed to be electrically connected to the CMOS circuitry. A memory array is formed over the bit line array. The memory array is formed by forming a word line stack, and forming first and second sets of stacked memory cells. The word line stack is formed on the bit line array and has a first side surface and a second side surface. The first sets of stacked memory cells are formed along the first side surface. The second sets of stacked memory cells are formed along the second side surface, wherein the second sets of stacked memory cells are staggered from the first sets of stacked memory cells. A source line array is formed over the memory array and electrically connected to the CMOS circuitry.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: December 12, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Hsuan Chien, Meng-Han Lin, Han-Wei Wu, Feng-Cheng Yang
  • Patent number: 11843016
    Abstract: An image sensor includes a semiconductor substrate of first conductivity type having first and second surfaces and including pixel regions, photoelectric conversion regions of second conductivity type respectively provided in the pixel regions, and a pixel isolation structure disposed in the semiconductor substrate to define the pixel regions and surrounding each of the photoelectric conversion regions. The pixel isolation structure includes a semiconductor pattern extending from the first surface to the second surface of the semiconductor substrate, a sidewall insulating pattern between a sidewall of the semiconductor pattern and the semiconductor substrate, and a dopant region in at least a portion of the semiconductor pattern.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: December 12, 2023
    Inventor: Jingyun Kim
  • Patent number: 11837517
    Abstract: A semiconductor device package is provided. The semiconductor device package includes a semiconductor device, a molding material surrounding the semiconductor device, and a conductive slot positioned over the molding material. The conductive slot has an opening and at least two channels connecting the opening to the edges of the conductive slot, and at least two of the channels extend in different directions.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Hua Yu, Hao-Yi Tsai, Tzu-Sung Huang, Ming-Hung Tseng, Hung-Yi Kuo
  • Patent number: 11839085
    Abstract: Provided are a three-dimensional vertical single transistor ferroelectric memory and a manufacturing method thereof. The ferroelectric memory comprises: a substrate; an insulating dielectric layer provided at the substrate; a channel structure extending through the insulating dielectric layer and connected to the substrate, the channel structure having a source/drain region and a channel region connected to the source/drain region; and a gate stack structure arranged around the channel structure and provided in the insulating dielectric layer opposite to the channel region, the gate stack structure comprising a ferroelectric insulation layer and a gate sequentially stacked in a direction away from the channel structure. The ferroelectric memory having the above structure can replace conventional DRAMs. Therefore, the invention realizes a high intensity high speed memory.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: December 5, 2023
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huaxiang Yin, Zhaozhao Hou, Tianchun Ye, Chaolei Li
  • Patent number: 11837583
    Abstract: A display device including a pixel circuit, an insulation layer covering the pixel circuit, an etching prevention layer disposed on the insulation layer, a first guide layer, a second guide layer, a first electrode, a second electrode, and a light emitting element. The first guide layer and the second guide layer may be disposed on the etching prevention layer and spaced apart from each other. The first electrode may be disposed on the first guide layer and electrically connected to the pixel circuit. The second electrode may be disposed on the first guide layer and insulated from the first electrode. The light emitting element may be in contact with the top surface of the etching prevention layer, disposed between the first guide layer and the second guide layer on a plane, and electrically connected to the first electrode and the second electrode.
    Type: Grant
    Filed: November 5, 2021
    Date of Patent: December 5, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Euikang Heo, Cha-Dong Kim, Hyunae Kim, Chongsup Chang