Patents Examined by Matthew E. Warren
  • Patent number: 11569176
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising multiple encapsulating layers and multiple signal distribution structures, and a method of manufacturing thereof.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: January 31, 2023
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Yi Seul Han, Tae Yong Lee, Ji Yeon Ryu
  • Patent number: 11557700
    Abstract: An optoelectronic semiconductor component includes a primary light source including a carrier and a semiconductor layer sequence mounted thereon and configured to generate primary light, and at least one conversion unit of at least one semiconductor material adapted to convert the primary light into at least one secondary light, wherein the semiconductor layer sequence and the converter unit are separate elements, the semiconductor layer sequence includes a plurality of pixels, the pixels are configured to be controlled electrically independently of each other, the carrier includes a plurality of control units configured to drive the pixels, all pixels of a first group are free of a conversion unit and are configured to emit the primary light, all pixels of a second group of pixels include exactly one conversion unit each and are configured to emit the at least one secondary light.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: January 17, 2023
    Assignee: OSRAM OLED GmbH
    Inventors: Isabel Otto, Alexander F. Pfeuffer, Britta Göötz, Norwin von Malm
  • Patent number: 11545506
    Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: January 3, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Bhagwati Prasad, Joyeeta Nag, Seung-Yeul Yang, Adarsh Rajashekhar, Raghuveer S. Makala
  • Patent number: 11545369
    Abstract: An electronic component includes a lead frame; a semiconductor chip arranged above the lead frame; and a connection layer sequence arranged between the lead frame and the semiconductor chip, wherein the connection layer sequence includes a first intermetallic layer including gold and indium or gold, indium and tin, a second intermetallic layer including indium and a titanium compound, indium and nickel, indium and platinum or indium and titanium, and a third intermetallic layer including indium and gold.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: January 3, 2023
    Assignee: OSRAM OLED GmbH
    Inventors: Mathias Wendt, Andreas Weimar
  • Patent number: 11532634
    Abstract: A nonvolatile memory device comprises a first semiconductor layer including, an upper substrate, and a memory cell array in which a plurality of word lines on the upper substrate extend in a first direction and a plurality of bit lines extend in a second direction. The nonvolatile memory device comprises a second semiconductor layer under the first semiconductor layer in a third direction perpendicular to the first and second directions, the second semiconductor layer including, a lower substrate, and a substrate control circuit on the lower substrate and configured to output a bias voltage to the upper substrate. The second semiconductor layer is divided into first through fourth regions, each of the first through fourth regions having an identical area, and the substrate control circuit overlaps at least a portion of the first through fourth regions in the third direction.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: December 20, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-won Shim, Bong-soon Lim
  • Patent number: 11532343
    Abstract: 3D memory arrays including dummy conductive lines and methods of forming the same are disclosed. In an embodiment, a memory array includes a ferroelectric (FE) material over a semiconductor substrate, the FE material including vertical sidewalls in contact with a word line; an oxide semiconductor (OS) layer over the FE material, the OS layer contacting a source line and a bit line, the FE material being between the OS layer and the word line; a transistor including a portion of the FE material, a portion of the word line, a portion of the OS layer, a portion of the source line, and a portion of the bit line; and a first dummy word line between the transistor and the semiconductor substrate, the FE material further including first tapered sidewalls in contact with the first dummy word line.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Chao-I Wu, Sheng-Chen Wang, Yu-Ming Lin
  • Patent number: 11532641
    Abstract: A semiconductor device includes: a stack structure including conductive patterns and insulating layers, which are alternately stacked; a channel structure penetrating the stack structure; and a memory layer penetrating the stack structure, the memory layer being disposed between the channel structure and the stack structure. The memory layer includes memory parts and dummy parts, which are alternately arranged. Each of the memory parts includes a first part between the insulating layers and a second part between the dummy parts. The first part of the memory parts have ferroelectricity.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: December 20, 2022
    Assignee: SK hynix Inc.
    Inventor: In Ku Kang
  • Patent number: 11527552
    Abstract: A ferroelectric memory device includes a multi-layer stack, a channel layer and a III-V based ferroelectric layer. The multi-layer stack is disposed on a substrate and includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers of the multi-layer stack. The III-V based ferroelectric layer is disposed between the channel layer and the multi-layer stack, and includes at least one element selected from Group III elements, at least one element selected from Group V elements, and at least one element selected from transition metal elements.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Chieh Lu, Sai-Hooi Yeong, Yu-Ming Lin, Mauricio Manfrini, Georgios Vellianitis
  • Patent number: 11527542
    Abstract: A semiconductor device includes: a substrate; a first dielectric layer over the substrate; a memory cell over the substrate in a first region of the semiconductor device, where the memory cell includes a first ferroelectric structure in the first dielectric layer, where the first ferroelectric structure includes a first bottom electrode, a first top electrode, and a first ferroelectric layer in between; and a tunable capacitor over the substrate in a second region of the semiconductor device, where the tunable capacitor includes a second ferroelectric structure, where the second ferroelectric structure includes a second bottom electrode, a second top electrode, and a second ferroelectric layer in between, where at least a portion of the second ferroelectric structure is in the first dielectric layer.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: December 13, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sai-Hooi Yeong, Chi On Chui, Chenchen Jacob Wang
  • Patent number: 11527553
    Abstract: In an embodiment, a device includes: a word line extending in a first direction; a data storage layer on a sidewall of the word line; a channel layer on a sidewall of the data storage layer; a back gate isolator on a sidewall of the channel layer; and a bit line having a first main region and a first extension region, the first main region contacting the channel layer, the first extension region separated from the channel layer by the back gate isolator, the bit line extending in a second direction, the second direction perpendicular to the first direction.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: December 13, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 11515353
    Abstract: Multicolor, stacked detector devices, focal plane arrays including multicolor, stacked detector devices, and methods of fabricating the same are disclosed. In one embodiment, a stacked multicolor detector device includes a first detector and a second detector. The first detector includes a first detector structure and a first ground plane adjacent the first detector structure. The second detector includes a second detector structure and a second ground plane adjacent the second detector structure. At least one of the first ground plane and the second ground plane is transmissive to radiation in a predetermined spectral band. The first detector and the second detector are in a stacked relationship.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: November 29, 2022
    Assignee: L3 CINCINNATI ELECTRONICS CORPORATION
    Inventors: Daniel Chmielewski, Yajun Wei, Nansheng Tang, Darrel Endres, Michael Garter, Mark Greiner
  • Patent number: 11515473
    Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer over a transistor region, where N is a natural number, and a bottom electrode over the Nth metal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1)th metal layer over the top electrode. The first width is greater than the third width.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: November 29, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Harry-Hak-Lay Chuang, Shih-Chang Liu, Chern-Yow Hsu, Kuei-Hung Shen
  • Patent number: 11515313
    Abstract: A gated ferroelectric memory cell includes a dielectric material layer disposed over a substrate, a metallic bottom electrode, a ferroelectric dielectric layer contacting a top surface of the bottom electrode, a pillar semiconductor channel overlying the ferroelectric dielectric layer and capacitively coupled to the metallic bottom electrode through the ferroelectric dielectric layer, a gate dielectric layer including a horizontal gate dielectric portion overlying the ferroelectric dielectric layer and a tubular gate dielectric portion laterally surrounding the pillar semiconductor channel, a gate electrode strip overlying the horizontal gate dielectric portion and laterally surrounding the tubular gate dielectric portion and a metallic top electrode contacting a top surface of the pillar semiconductor channel.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: November 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Bo-Feng Young, Sai-Hooi Yeong, Han-Jong Chia, Sheng-Chen Wang, Yu-Ming Lin
  • Patent number: 11508732
    Abstract: A semiconductor device includes bit line structures disposed on a substrate, each bit line structure comprising a bit line and an insulating spacer structure, buried contacts which fill lower portions of spaces between bit line structures in the substrate, and landing pads which fill upper portions of the spaces, extend from upper surfaces of the buried contacts to upper surfaces of the bit line structures, and are spaced apart from each other by insulating structures. A first insulating structure is disposed between a first landing pad and a first bit line structure. The first insulating structure includes a sidewall extending along a sidewall of the first landing pad toward the substrate. In a direction extending toward the substrate, the sidewall of the first insulating structure gets closer to a first sidewall of the first bit line structure.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: November 22, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jihee Kim, Yeongshin Park, Hyunchul Yoon, Joonghee Kim, Jungheun Hwang
  • Patent number: 11502179
    Abstract: Some embodiments include a ferroelectric transistor having an active region which includes a first source/drain region, a second source/drain region vertically offset from the first source/drain region, and a channel region between the first and second source/drain regions. A first conductive gate is operatively adjacent to the channel region of the active region. Insulative material is between the first conductive gate and the channel region. A second conductive gate is adjacent to the first conductive gate. Ferroelectric material is between the first and second conductive gates. Some embodiments include integrated memory. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: November 15, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Pankaj Sharma
  • Patent number: 11502084
    Abstract: A three-dimensional semiconductor memory device includes first semiconductor patterns, which are vertically spaced apart from each other on a substrate, each of which includes first and second end portions spaced apart from each other, and first and second side surfaces spaced apart from each other to connect the first and second end portions, first and second source/drain regions disposed in each of the first semiconductor patterns and adjacent to the first and second end portions, respectively, a channel region in each of the first semiconductor patterns and between the first and second source/drain regions, a first word line adjacent to the first side surfaces and the channel regions and vertically extended, and a gate insulating layer interposed between the first word line and the first side surfaces. The gate insulating layer may be extended to be interposed between the first source/drain regions.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: November 15, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joongchan Shin, Changkyu Kim, Hui-Jung Kim, Iljae Shin, Taehyun An, Kiseok Lee, Eunju Cho, Hyungeun Choi, Sung-Min Park, Ahram Lee, Sangyeon Han, Yoosang Hwang
  • Patent number: 11502157
    Abstract: A display panel includes: a substrate including: a first region; a second region; a non-display area surrounding the first region and the second region; and a display area surrounding the non-display area; a plurality of pixels in the display area; a plurality of wirings configured to supply signals to the plurality of pixels; a load matching area connected to first wirings of the wirings, the load matching area including load units in the non-display area; and a dummy area including a plurality of dummy units spaced apart from the load units in the non-display area, wherein each of the load units comprises a load semiconductor layer, a first load conductive layer, and a second load conductive layer which at least partially overlap each other with an insulating layer therebetween, and the load semiconductor layer is connected to the second load conductive layer via a first contact hole.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: November 15, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jisu Na, Yangwan Kim, Minwoo Byun
  • Patent number: 11495618
    Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: November 8, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Feng-Cheng Yang, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 11488868
    Abstract: The present disclosure relates to a FinFET structure and a method of manufacturing the same. The FinFET structure includes a first fin and a second fin. The first fin is over a first base and has a first channel region. The first channel region has a first channel length. The second fin is over a second base and has a second channel region. The second channel region has a second channel length. The second channel length is different from the first channel length.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: November 1, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chun-Heng Wu
  • Patent number: 11488878
    Abstract: Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate and to provide probing structures (or pads). Testing structures, including daisy-chain structures, with metal lines to connect bonding structures connected to signals, power source, and/or grounding structures are connected to probing structures on the interconnect substrate. The testing structures enable determining the quality of bonding and/or functionalities of packaged dies bonded. After electrical testing is completed, the metal lines connecting the probing structures and the bonding structures are severed to allow proper function of devices in the die package. The mechanisms for forming test structures with probing pads on interconnect substrate and severing connecting metal lines after testing could reduce manufacturing cost.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: November 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Hua Chen, Chen-Shien Chen, Ching-Wen Hsiao