Abstract: A stress enhanced CMOS circuit and methods for its fabrication are provided. One fabrication method comprises the steps of forming an NMOS transistor and a PMOS transistor adjacent the NMOS transistor in a channel width direction, the PMOS transistor and the NMOS transistor separated by an isolation region. A compressive stress liner is deposited overlying the transistors and the isolation region and is etched to remove the compressive stress liner from the NMOS transistor and from a portion of the isolation region. A tensile stress liner is deposited overlying the transistors, the isolation region, and the compressive stress liner and is etched to remove a portion of the tensile stress liner overlying a portion of the compressive stress liner and to leave the tensile stress liner overlying the NMOS transistor, the isolation region, and a portion of the compressive stress liner.

Abstract: Disclosed is an integrated circuit structure that has a substrate having at least two types of crystalline orientations. First-type transistors (e.g., NFETs) are formed on first portions of the substrate having a first type of crystalline orientation, and second-type transistors (e.g., PFETs) are formed on second portions of the substrate having a second type of crystalline orientation. Some of the first portions of the substrate comprise non-floating substrate portions, and the remaining ones of the first portions and all of the second portions of the substrate comprise floating substrate portions.

Abstract: A light-emitting diode (LED) and a method for manufacturing the same are described. The method for manufacturing the LED comprises the following steps. An illuminant epitaxial structure is provided, in which the illuminant epitaxial structure has a first surface and a second surface on opposite sides, and a substrate is deposed on the first surface of the illuminant epitaxial structure. A metal layer is formed on the second surface of the illuminant epitaxial structure. An anodic oxidization step is performed to oxidize the metal layer, so as to form a metal oxide layer. An etching step is performed to remove a portion of the metal oxide layer, so as to form a plurality of holes in the metal oxide layer.

Abstract: A method for making a semiconductor device having non-volatile memory cell transistors and transistors of another type is provided. In the method, a substrate is provided having an NVM region, a high voltage (HV) region, and a low voltage (LV) region. The method includes forming a gate dielectric layer on the HV and LV regions. A tunnel oxide layer is formed over the substrate in the NVM region and the gate dielectric in the HV and LV regions. A first polysilicon layer is formed over the tunnel dielectric layer and gate dielectric layer. The first polysilicon layer is patterned to form NVM floating gates. An ONO layer is formed over the first polysilicon layer. A single etch removal step is used to form gates for the HV transistors from the first polysilicon layer while removing the first polysilicon layer from the LV region.

Abstract: In a liquid crystal display device substrate, an insulating layer covers a thin film transistor. Another insulating layer covers a black matrix, which is formed on the insulating layer and covers the thin film transistor, a gate line, and a data line except a portion of a drain electrode. A first transparent conductive layer covers the top insulating layer and contacts the exposed portions of the drain electrode, a gate pad and a data pad. A buffer layer is formed on the first conductive layer and a color filter is formed on the buffer layer. The buffer layer is exposed by the color filter to reveal portions of the first conductive layer. A second transparent conductive layer covers the color filter and the revealed portions of the first conductive layer. The conductive layers are patterned to form pixel electrodes and double-layered gate and data pad terminals.

Abstract: A floating gate non-volatile memory is composed of a semiconductor substrate within which active regions and isolation dielectrics are alternately arranged in a first direction; a word line extending in the first direction to intersect with the active regions and the isolation dielectrics; a plurality of floating gates disposed between the respective active regions and the word lines; and a plurality of contacts connected with diffusion layers formed within the active regions, respectively, the plurality of contacts being arranged in the first direction. The plurality of contacts include drain contacts and a source contact, and the diffusion layers includes drain diffusion layers connected with the drain contacts and a source diffusion layer connected with the source contact. The semiconductor substrate incorporates a conductive source region extending in the first direction, and an embedded diffusion layer. The source region is positioned opposing the plurality of contacts across the word line.

Abstract: A semiconductor package mainly includes a chip, a substrate, an encapsulant, a plurality of external terminals and a stress release layer. The substrate has an upper surface and a lower surface. The chip is disposed on the upper surface of the substrate by a chip-attached layer and electrically connected to the substrate. The encapsulant is formed above the upper surface of the substrate. The external terminals are disposed on the lower surface of the substrate. The stress release layer is formed on the interface of the substrate and the encapsulant such that the external terminals are movable with respect to the encapsulated chip. In addition, a fabrication process of the semiconductor package is also disclosed.

Abstract: A CMOS image sensor-manufacturing method includes forming a photodiode on a substrate, forming an insulating layer over the substrate, forming a contact hole in the insulating layer, and forming a gate terminal over the insulating layer. The gate terminal is connected to the photodiode through the contact hole.

Abstract: A method for fabricating a pixel structure is provided. First, a gate, a scan line, and a first terminal are formed on a substrate. A gate insulating layer is formed over the substrate to cover the gate, the scan line, and the first terminal. After defining the semiconductor layer, the gate insulating layer is patterned to exposure the first terminal. A transparent conductive layer is formed over the substrate and a patterned photoresist layer is formed on the transparent conductive layer. The transparent conductive layer is patterned using the patterned photoresist layer as a mask, so as to define a source, a drain, a data line, a pixel electrode, a second terminal, and a contact pad. Because only four photomasks are used to implement the above method for fabricating the pixel structure, the cost of manufacturing can be reduced.

Abstract: A gate insulating film is formed on the principal surface of a semiconductor substrate. A silicon film is formed on the gate insulating film. Impurities are doped in the silicon film. In this case, impurities are doped into the silicon film to make a region of the silicon film in the memory cell area have a first impurity concentration and to make a region of the silicon film in the logic circuit area have a second impurity concentration lower than the first impurity concentration. The doped silicon film is patterned. In this case, the silicon film is patterned to leave word lines having the first impurity concentration and serving as gate electrodes in the memory cell area and to leave gate electrodes having the second impurity concentration in the logic circuit area.

Abstract: According to the present invention, there is provided a semiconductor device fabrication method comprising: measuring light emission intensity of at least one type of wavelength contained in light emitted from a plasma, when one of nitriding, oxidation, and impurity doping is to be performed on a surface of a semiconductor substrate in a processing vessel by using the plasma; calculating, for each semiconductor substrate, an exposure time during which the semiconductor substrate is exposed to the plasma, on the basis of the measured light emission intensity; and exposing each semiconductor substrate to the plasma on the basis of the calculated exposure time, thereby performing one of the nitriding, oxidation, and impurity doping.

Abstract: A small-size (w<0.5 micrometers) alignment mark in combination with a “k1 process” is proposed, which is particularly suited for the fabrication of trench-capacitor DRAM devices which requires highly accurate AA-DT alignment. The “k1 process” is utilized to etch away polysilicon studded in the alignment mark trenches and refresh the trench profile prior to AA pattern transferring, thereby improving wafer alignment accuracy and precision.

Abstract: Methods are provided for fabricating a stress enhanced MOS circuit. One method comprises the steps of depositing a stressed material overlying a semiconductor substrate and patterning the stressed material to form a stressed dummy gate electrode overlying a channel region in the semiconductor substrate so that the stressed dummy gate induces a stress in the channel region. Regions of the semiconductor substrate adjacent the channel are processed to maintain the stress to the channel region and the stressed dummy gate electrode is replaced with a permanent gate electrode.

Abstract: By forming a copper/silicon/nitrogen alloy in a surface portion of a copper-containing region on the basis of a precursor layer, highly controllable and reliable process conditions may be established. The precursor layer may be formed on the basis of a liquid precursor solution, which may exhibit a substantially self-aligned and self-limiting deposition behavior.

Abstract: A process for forming a catalyst layer for carbon nanotube growth comprising forming a catalyst layer having a first and second portion over one of a cathode metal layer or a ballast resistor layer; patterning a photoresist over the first portion; etching the second portion with a chlorine/argon plasma; removing the photoresist with an ash process; and removing the veils and preparing the surface for carbon nanotube growth with a semi-aqueous hydroxylamine solution.

Abstract: Various structures having a dielectric film containing Zr—Sn—Ti—O formed by atomic layer deposition using a TiI4 precursor and a method of fabricating structures having such a dielectric film produce the structures with a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO2. Dielectric films containing Zr—Sn—Ti—O formed by atomic layer deposition using TiI4 are thermodynamically stable such that the Zr—Sn—Ti—O will have minimal reactions with a silicon substrate or other structures during processing.

Abstract: A method for forming TGO structures includes providing a substrate containing regions of first, second and third kinds in which devices with respective first, second and third gate oxide layers of different thicknesses are to be formed. The second gate oxide layer is formed over the substrate and then removed from regions of the first kind where the first gate oxide layer is subsequently grown. A first conductive layer is deposited over the substrate. The first conductive layer and second gate oxide layer are subsequently removed from regions of the third kind. The third gate oxide layer followed by deposition of a second conductive layer is formed over the substrate and then removed except from over regions of the third kind.

Abstract: The invention provides an inspection apparatus and an inspection method for detecting defects, a punching apparatus, and a method for controlling a punching apparatus, for the purpose of immediate detection of debris from being lifted toward the surface of an insulating film for film carrier tape, which debris tends to occur during punching of the insulating film for film carrier tape by use of a punching mold, whereby the number of pieces having defects on the film surface caused by attachment of debris from being lifted or foreign matter is reduced to a minimum possible number.

Abstract: Methods are provided for depositing amorphous carbon materials. In one aspect, the invention provides a method for processing a substrate including positioning the substrate in a processing chamber, introducing a processing gas into the processing chamber, wherein the processing gas comprises a carrier gas, hydrogen, and one or more precursor compounds, generating a plasma of the processing gas by applying power from a dual-frequency RF source, and depositing an amorphous carbon layer on the substrate.

Abstract: A method for producing from a plate-shaped substrate circular sections for use for instance in a color wheel encompasses inter alia such steps as positioning predefined edge break lines in such fashion that the circular sections to be separated at a subsequent point are arranged in columns, with the circular sections within a column being so positioned relative to one another that in each case at least certain points of the inner annular edge are in contact with the outer annular edge of another circular section, thus forming part of a common predefined edge break line, while the orientation of the curvature of the circular sections of neighboring columns is reversed in alternating fashion. In a subsequent step the circular sections are separated along the predefined edge break lines.