Abstract: A wafer level package, and a semiconductor wafer, electronic system, and a memory module that include one or more of the wafer level packages, and methods of fabricating the die packages on a wafer level, and integrated circuit modules that include one or more packages are provided. In one embodiment, the die package comprises a redistribution layer interconnecting two or more dies disposed on a substrate, typically a semiconductor wafer, the redistribution layer including a first trace connecting a bond pad of each of two dies, and a second trace connecting one of the bond pads of the two dies to a ball pad. The die package of the invention can comprise memory devices such as static random access memories (SRAMs), and can be incorporated into a variety of electronic systems as part of a memory package such as single in line memory modules (SIMMs) or dual in line memory modules.

Abstract: A method is provided for forming an interconnect in a semiconductor memory device. The method includes forming a pair of source select transistors on a substrate. A source region is formed in the substrate between the pair of source select transistors. A first inter-layer dielectric is formed between the pair of source select transistors. A mask layer is deposited over the pair of source select transistors and the inter-layer dielectric, where the mask layer defines a local interconnect area between the pair of source select transistors having a width less than a distance between the pair of source select transistors. The semiconductor memory device is etched to remove a portion of the first inter-layer dielectric in the local interconnect area, thereby exposing the source region. A metal contact is formed in the local interconnect area.

Abstract: A method for fabricating a floating gate memory device comprises using a buried diffusion oxide that is below the floating gate thereby producing an increased step height between the floating gate and the buried diffusion oxide. The increased step height can produce a higher GCR, while still allowing decreased cell size using a virtual ground array design.

Abstract: Methods of forming electrical interconnects include forming a copper pattern on a semiconductor substrate and then forming an electrically insulating capping layer on the copper pattern and an interlayer insulating layer on the electrically insulating capping layer. A contact hole is then formed, which extends through the interlayer insulating layer and the electrically insulating capping layer and exposes an upper surface of the copper pattern. An electroless plating step is then performed to form a copper pattern extension onto the exposed upper surface of the copper pattern. The copper pattern extension may have a thickness that is less than a thickness of the electrically insulating capping layer, which may be formed as a SiCN layer.

Abstract: An integrated circuit (IC) fabrication technique is provided for isolating very high voltage (1000s of volts) circuitry and low voltage circuitry formed on the same semiconductor die. Silicon-on-Insulator (SOI) technology is combined with a pair of adjacent backside high voltage isolation trenches that are fabricated to be wide enough to stand off voltages in excess of 1000V. The lateral trench is fabricated at two levels: the active silicon level and at the wafer backside in the SOI bulk.

Abstract: A method of operating and process for fabricating an electron source. A conductive rod is covered by an insulating layer, by dipping the rod in an insulation solution, for example. The rod is then covered by a field emitter material to form a layered conductive rod. The rod may also be covered by a second insulating material. Next, the materials are removed from the end of the rod and the insulating layers are recessed with respect to the field emitter layer so that a gap is present between the field emitter layer and the rod. The layered rod may be operated as an electron source within a vacuum tube by applying a positive bias to the rod with respect to the field emitter material and applying a higher positive bias to an anode opposite the rod in the tube. Electrons will accelerate to the charged anode and generate soft X-rays.

Abstract: A photovoltaic device including a rear electrode which may also function as a rear reflector. In certain example embodiments of this invention, the rear electrode includes a metallic based reflective film that is oxidation graded, so as to be more oxided closer to a rear substrate (e.g., glass substrate) supporting the electrode than at a location further from the rear substrate. In other words, the rear electrode is oxidation graded so as to be less oxided closer to a semiconductor absorber of the photovoltaic device than at a location further from the semiconductor absorber in certain example embodiments. In certain example embodiments, the interior surface of the rear substrate may optionally be textured so that the rear electrode deposited thereon is also textured so as to provide desirable electrical and reflective characteristics. In certain example embodiments, the rear electrode may be of or include Mo and/or MoOx, and may be sputter-deposited using a combination of MoOx and Mo sputtering targets.

Abstract: A semiconductor having an optimized insulation structure which is simple and inexpensive to produce and can be made smaller than LOCOS insulation structures is disclosed. An implantation mask on a surface of a semiconductor substrate is used to implant elements into the semiconductor substrate, which elements, on thermal activation, form an insulation region together with the further elements of the semiconductor substrate. The thermal activation is effected by means of laser irradiation, during which the semiconductor substrate is briefly melted and then recrystallizes during the subsequent cooling, so that the implanted elements form the insulation region together with the further elements of the semiconductor substrate.

Abstract: A method of manufacturing a pixel structure is provided. A first patterned conductive layer including a gate and a data line is formed on a substrate. A gate insulating layer is formed to cover the first patterned conductive layer and a semiconductor channel layer is formed on the gate insulating layer above the gate. A second patterned conductive layer including a scan line, a common line, a source and a drain is formed on the gate insulating layer and the semiconductor channel layer. The scan line is connected to the gate and the common line is located above the data line. The source and drain are located on the semiconductor channel layer, and the source is connected to the data line. A passivation layer is formed on the substrate to cover the second patterned conductive layer. A pixel electrode connected to the drain is formed on the passivation layer.

Abstract: A semiconductor structure and a system for fabricating an integrated circuit chip. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa. The system for fabricating an integrated circuit chip enables: providing a buried oxide layer on and in direct mechanical contact with a semiconductor wafer; and concurrently forming at least one fin-type field effect transistor and at least one thick-body device on the buried oxide layer.

Abstract: A semiconductor device is disclosed that stably ensures an area of a storage node contact connected to a junction region in an active region of the semiconductor device and is thus able to improve the electrical properties of the semiconductor device and enhance a yield, and a method for fabricating the same. The semiconductor device includes a semiconductor substrate having an active region including a gate, a storage node contact region, and an isolation region that defines the active region. A passing gate and an isolation structure surrounding the passing gate are formed in the isolation region. A silicon epitaxial layer is selectively formed over an upper portion of the passing gate to expand the storage node contact region.

Abstract: A one-step diffusion method for fabricating a differential doped solar cell is described. The one-step diffusion method includes the following step. First, a substrate is provided. A doping control layer is formed on the substrate. The doping control layer includes a plurality of openings therein.

Abstract: A manufacturing method for electronic device, includes: preparing a first substrate having a plurality of first regions; preparing a second substrate having a plurality of second regions; facing the first region and the second region each other, and connecting the first substrate and the second substrate while disposing at least a part of a functional element within a space between the first region and the second region; obtaining a plurality of first divisional substrates by cutting the first substrate at each of the first regions, after the connecting of the first substrate and the second substrate; forming a sealing film covering the plurality of the first divisional substrates on the second substrate, after cutting the first substrate; obtaining a plurality of second divisional substrates by cutting the second substrate at each of the second regions, after forming the sealing film; and obtaining a plurality of individual electronic devices.

Abstract: A method for manufacturing a nitride semiconductor substrate including the steps of: forming a nitride semiconductor layer on a sapphire substrate, and manufacturing a freestanding nitride semiconductor substrate by using the nitride semiconductor layer separated from the sapphire substrate, wherein variability of inclinations of the C-axes, being a difference between a maximum value and a minimum value of inclination of the C-axes in a radially-outward direction at each point on a front surface of the sapphire substrate is 0.3° or more and 1° or less.

Abstract: A semiconductor laser using a nitride type Group III-V compound semiconductor includes: an n-side clad layer; an n-side optical waveguide layer over the n-side clad layer; an active layer over the n-side optical waveguide layer; a p-side optical waveguide layer over the active layer; an electron barrier layer over the p-side optical waveguide layer; and a p-side clad layer over the electron barrier layer. A ridge stripe is formed at an upper part of the p-side optical waveguide layer, the electron barrier layer and the p-side clad layer, and the distance between the electron barrier layer and a bottom surface in areas on both sides of the ridge stripe is not less than 10 nm.

Abstract: A nonvolatile memory integrated circuit has a semiconductor substrate and a nonvolatile memory device on the semiconductor substrate. The device has a transistor and a capacitor on the semiconductor substrate, and a shared floating gate connecting the gate regions of the transistor and the capacitor. The transistor has at least a doping region defining the source and drain regions, as well as three other doping regions overlapping the source and drain regions. Also disclosed are a nonvolatile memory circuit with multiple such nonvolatile memory device, and methods for making the nonvolatile memory circuit with one or more such nonvolatile memory devices.

Abstract: A method of forming an ohmic contact layer including forming an insulation layer pattern on a substrate, the insulation pattern layer having an opening selectively exposing a silicon bearing layer, forming a metal layer on the exposed silicon bearing layer using an electrode-less plating process, and forming a metal silicide layer from the silicon bearing layer and the metal layer using a silicidation process. Also, a method of forming metal wiring in a semiconductor device using the foregoing method of forming an ohmic contact layer.

Abstract: A processing chamber is seasoned by providing a flow of season precursors to the processing chamber. A high-density plasma is formed from the season precursors by applying at least 7500 W of source power distributed with greater than 70% of the source power at a top of the processing chamber. A season layer having a thickness of at least 5000 ? is deposited at one point using the high-density plasma. Each of multiple substrates is transferred sequentially into the processing chamber to perform a process that includes etching. The processing chamber is cleaned between sequential transfers of the substrates.

Abstract: The main object of the present invention is to provide a method for manufacturing efficiently a pattern formed structure which has a surface having a property-varied pattern and can be used to manufacture a color filter or the like. In order to achieve the object, the present invention provides a method for manufacturing a pattern formed structure, comprising: a patterning substrate preparing process of preparing a patterning substrate having a base material and a property variable layer which is formed on the base material and has a property variable by action of a photocatalyst based on irradiation with energy; and an energy radiating process of arranging a photocatalyst containing layer side substrate having a base body and a photocatalyst containing layer comprising at least the photocatalyst, and the patterning substrate so as to keep a given interval between the photocatalyst containing layer and the property variable layer, and then radiating energy onto the resultant at an intensity of 0.

Abstract: A method for depositing a carbon doped epitaxial semiconductor layer comprises maintaining a pressure of greater than about 700 torr in a process chamber housing a patterned substrate having exposed single crystal material. The method further comprises providing a flow of a silicon source gas to the process chamber. The silicon source gas comprises dichlorosilane. The method further comprises providing a flow of a carbon precursor to the process chamber. The method further comprises selectively depositing the carbon doped epitaxial semiconductor layer on the exposed single crystal material.