Patents Examined by Matthew W. Such
  • Patent number: 9515175
    Abstract: A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. In a semiconductor device including a bottom-gate transistor in which an insulating layer functioning as a channel protective film is provided over an oxide semiconductor film, elements contained in an etching gas can be prevented from remaining as impurities on a surface of the oxide semiconductor film by performing impurity-removing process after formation of an insulating layer provided over and in contact with the oxide semiconductor film and/or formation of source and drain electrode layers. The impurity concentration in the surface of the oxide semiconductor film is lower than or equal to 5×1018 atoms/cm3, preferably lower than or equal to 1×1018 atoms/cm3.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: December 6, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Katsuaki Tochibayashi, Satoshi Higano, Shunpei Yamazaki
  • Patent number: 9472675
    Abstract: This disclosure relates to a method of manufacturing n-doped graphene and an electrical component using ammonium fluoride (NH4F), and to graphene and an electrical component thereby. An example method of manufacturing n-doped graphene includes (a) preparing graphene and ammonium fluoride (NH4F); and (b) exposing the graphene to the ammonium fluoride (NH4F), wherein through (b), a fluorine layer is formed on part or all of upper and lower surfaces of a graphene layer, and ammonium ions are physisorbed to part or all of the upper and lower surfaces of the graphene layer or defects between carbon atoms of the graphene layer, thereby maintaining or further improving superior electrical properties of graphene including charge mobility while performing n-doping of graphene.
    Type: Grant
    Filed: April 18, 2014
    Date of Patent: October 18, 2016
    Assignees: Korea Advanced Institute of Science and Technology, Lam Research Corporation
    Inventors: Byung Jin Cho, Jae Hoon Bong, Onejae Sul, Hyungsuk Alexander Yoon
  • Patent number: 9466711
    Abstract: Between a source electrode (25) of a main device (24) and a current sensing electrode (22) of a current detection device (21), a resistor for detecting current is connected. Dielectric withstand voltage of gate insulator (36) is larger than a product of the resistor and maximal current flowing through the current detection device (21) with reverse bias. A diffusion length of a p-body region (32) of the main device (24) is shorter than that of a p-body (31) of the current detection device (21). A curvature radius at an end portion of the p-body region (32) of the main device (24) is smaller than that of the p-body (31) of the current detection device (21). As a result, at the inverse bias, electric field at the end portion of the p-body region (32) of the main device (24) becomes stronger than that of the p-body region (31) of the current detection device (21). Consequently, avalanche breakdown tends to occur earlier in the main device 24 than the current detection device (21).
    Type: Grant
    Filed: January 28, 2009
    Date of Patent: October 11, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Seiji Momota, Hitoshi Abe, Takashi Shiigi, Takeshi Fujii, Koh Yoshikawa, Tetsutaro Imagawa, Masaki Koyama, Makoto Asai
  • Patent number: 9466726
    Abstract: Provided is a bottom-gate transistor including an oxide semiconductor, in which electric-field concentration which might occur in the vicinity of an end portion of a drain electrode layer (and the vicinity of an end portion of a source electrode layer) when a high gate voltage is applied to a gate electrode layer is reduced and degradation of switching characteristics is suppressed, so that the reliability is improved. The cross-sectional shape of an insulating layer which overlaps over a channel formation region is a tapered shape. The thickness of the insulating layer which overlaps over the channel formation region is 0.3 ?m or less, preferably 5 nm or more and 0.1 ?m or less. The taper angle ? of a lower end portion of the cross-sectional shape of the insulating layer which overlaps over the channel formation region is 60° or smaller, preferably 45° or smaller, further preferably 30° or smaller.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: October 11, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiko Hayakawa, Satoshi Shinohara
  • Patent number: 9466710
    Abstract: A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a dielectric disposed on top of the gate electrode, and a doped polysilicon spacer disposed on the source region and along a sidewall of the dielectric. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: October 11, 2016
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: François Hébert, Anup Bhalla
  • Patent number: 9461164
    Abstract: A semiconductor device includes a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor device further includes first and second trenches extending from the first surface into the semiconductor body. The semiconductor device further includes at least one lateral IGFET including a first load terminal at the first surface, a second load terminal at the first surface and a gate electrode within the first trenches. The semiconductor device further includes at least one vertical IGFET including a first load terminal at the first surface, a second load terminal at the second surface and a gate electrode within the second trenches.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: October 4, 2016
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Meyer, Werner Schwetlick
  • Patent number: 9461041
    Abstract: A device including a substrate having a fin. A metal gate structure is formed on the fin. The metal gate structure includes a stress metal layer formed on the fin such that the stress metal layer extends to a first height from an STI feature, the first height being greater than the fin height. A conduction metal layer is formed on the stress metal layer.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: October 4, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Lin Yang, Tsu-Hsiu Perng, Chih Chieh Yeh, Li-Shyue Lai
  • Patent number: 9461079
    Abstract: An imager having a pixel cell having an associated strained silicon layer. The strained silicon layer increases charge transfer efficiency, decreases image lag, and improves blue response in imaging devices.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: October 4, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 9449977
    Abstract: A semiconductor device includes a substrate and a plurality of storage nodes on the substrate and extending in a vertical direction relative to the substrate. A lower support pattern is in contact with the storage nodes between a bottom and a top of the storage nodes, the lower support pattern spaced apart from the substrate in the vertical direction, and the lower support pattern having a first maximum thickness in the vertical direction. An upper support pattern is in contact with the storage nodes above the lower support pattern relative to the substrate, the upper support pattern spaced apart from the lower support pattern in the vertical direction, and the lower support pattern having a second maximum thickness in the vertical direction that is greater than the first maximum thickness of the lower support pattern.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: September 20, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: JungWoo Seo
  • Patent number: 9450061
    Abstract: A metal bump structure for use in a driver IC includes a passivation layer disposed on a metal pad and defining a recess on the metal pad, an adhesion layer in said recess, on the metal pad and on the passivation layer, a metal bump disposed in the recess and completely covering the adhesion layer, and a capping layer disposed on the metal bump and completely covering the metal bump so that the metal bump is not exposed to an ambient atmosphere.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: September 20, 2016
    Assignee: HIMAX TECHNOLOGIES LIMITED
    Inventor: Chiu-Shun Lin
  • Patent number: 9444016
    Abstract: Provided are a light emitting device, a light emitting device package, and a lighting system. The light emitting device comprises a reflective layer, a second conductive type semiconductor layer on the reflective layer, an active layer on the second conductive type semiconductor layer, a first conductive type semiconductor layer on the active layer, and a pad electrode on the first conductive type semiconductor layer. The reflective layer comprises a predetermined pattern.
    Type: Grant
    Filed: May 2, 2012
    Date of Patent: September 13, 2016
    Assignee: LG Innotek Co., Ltd.
    Inventors: Ho Sang Kwack, Hyun Soo Lim, Ju Hyon Song, Hyun Kyong Cho, Ho Ki Kwon
  • Patent number: 9444013
    Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, a p-side electrode, an n-side electrode, an insulating film, a p-side interconnection section, an n-side interconnection section, a phosphor layer, and a metal film. The semiconductor layer is formed on a substrate which is then removed. The p-side interconnection section is provided on the insulating film and electrically connected to the p-side electrode. The n-side interconnection section is provided on the insulating film and electrically connected to the n-side electrode. The phosphor layer is provided on the first surface and includes a step portion continued to the side surface of the semiconductor layer. The metal film is provided on the side surface of the semiconductor layer and a side surface of the step portion of the phosphor layer.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: September 13, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Miyoko Shimada, Akihiro Kojima, Yosuke Akimoto, Hideto Furuyama, Hideyuki Tomizawa, Yoshiaki Sugizaki
  • Patent number: 9443793
    Abstract: A first chip including electrodes is mounted above an expanded semiconductor chip formed by providing an expanded portion at an outer edge of a second chip including chips. The electrodes of the first chip are electrically connected to the electrodes of the second chip by conductive members. A re-distribution structure is formed from a top of the first chip outside a region for disposing the conductive members along a top of the expanded portion. Connection terminals are provided above the expanded portion, and electrically connected to ones of the electrodes of the first chip via the re-distribution structure.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: September 13, 2016
    Assignee: Panasonic Corporation
    Inventors: Hiroki Yamashita, Takashi Yui, Takeshi Kawabata, Kiyomi Hagihara, Kenji Yokoyama
  • Patent number: 9443961
    Abstract: An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first portion level with the semiconductor strip, and a second portion lower than the semiconductor strip. The second portion further includes a portion overlapped by the semiconductor strip.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: September 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Chun Huang, Chih-Tang Peng, Chia-Wei Chang, Ming-Hua Yu, Hao-Ming Lien, Chao-Cheng Chen, Tze-Liang Lee
  • Patent number: 9443941
    Abstract: A transistor device includes a compound semiconductor body having a first surface and a two-dimensional charge carrier gas disposed below the first surface in the compound semiconductor body. The transistor device further includes a source in contact with the two-dimensional charge carrier gas and a drain spaced apart from the source and in contact with the two-dimensional charge carrier gas. A first passivation layer is in contact with the first surface of the compound semiconductor body, and a second passivation layer is disposed on the first passivation layer. The second passivation layer has a different etch rate selectivity than the first passivation layer. A gate extends through the second passivation layer into the first passivation layer.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: September 13, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Häberlen, Gilberto Curatola
  • Patent number: 9437784
    Abstract: Disclosed is a light emitting device including a light emitting structure comprising a first semiconductor layer, an active layer and a second semiconductor layer, a phosphor plate disposed on the second semiconductor layer, a first electrode portion disposed on the phosphor plate, and a plurality of bonding portions disposed between the light emitting structure and the phosphor plate, the bonding portions bonding the phosphor plate to the light emitting structure, wherein each bonding portion includes at least one first bonding portion electrically connected to the first electrode portion.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 6, 2016
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Gun Kyo Lee
  • Patent number: 9431526
    Abstract: A heterostructure grown on a silicon substrate includes a single crystal rare earth oxide template positioned on a silicon substrate, the template being substantially crystal lattice matched to the surface of the silicon substrate. A heterostructure is positioned on the template and defines at least one heterojunction at an interface between a III-N layer and a III-III-N layer. The template and the heterostructure are crystal matched to induce an engineered predetermined tensile strain at the at least one heterojunction. A single crystal rare earth oxide dielectric layer is grown on the heterostructure so as to induce an engineered predetermined compressive stress in the single crystal rare earth oxide dielectric layer and a tensile strain in the III-III-N layer. The tensile strain in the III-III-N layer and the compressive stress in the REO layer combining to induce a piezoelectric field leading to higher carrier concentration in 2DEG at the heterojunction.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: August 30, 2016
    Assignee: TRANSLUCENT, INC.
    Inventors: Rytis Dargis, Andrew Clark, Erdem Arkun
  • Patent number: 9431577
    Abstract: This invention relates to relates to silicon light emitting devices (SiLEDs), and its application into current Complementary Metal Oxide Semiconductor (CMOS) technology, as well into future Silicon on Insulator (SOI) technology. According to the invention, a silicon based light emitting device is designed to operate by means of avalanche carrier multiplication and emitting at the below threshold wavelength detection range for Silicon of 850 nm and such that it is compatible with CMOS silicon nitride, silicon oxi-nitride and polymer waveguide technology. This favors diverse electro-optical system applications such as electro-optical couplers, fast data transfer on and from chip, various optical interconnect configurations as well as diverse on-chip sensor, fluidic and micro-optical-mechanical sensor applications. Under particular operating conditions emissions at specific wavelengths (for example the longer wavelengths) may be favored, while in other cases tuning of the emitted radiation may be obtained.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: August 30, 2016
    Assignee: Tshwane University of Technology
    Inventor: Lukas Willem Snyman
  • Patent number: 9425291
    Abstract: A semiconductor structure is provided that includes a plurality of suspended and stacked nanosheets of semiconductor channel material located above a pillar of a sacrificial III-V compound semiconductor material. Each semiconductor channel material comprises a semiconductor material that is substantially lattice matched to, but different from, the sacrificial III-V compound semiconductor material, and each suspended and stacked nanosheets of semiconductor channel material has a chevron shape. A functional gate structure can be formed around each suspended and stacked nanosheet of semiconductor channel material.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: August 23, 2016
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
  • Patent number: 9425326
    Abstract: Described herein is a method for forming a vertical memory device (150) having a vertical channel region (113) sandwiched between a source region (109, 112) and a drain region (114). A charge trapping layer (106) is provided either side of the vertical channel region (113) and associated source and drain regions (109, 112, 114). The source region (109, 112) comprises a junction between a first region (109) comprising a first doping type with a first doping concentration and a second region (112) comprising a second doping type which is opposite to the first doping type and with a second doping concentration. The drain region (114) comprises the first doping type with a first doping concentration. In another embodiment, the drain region has two regions of differing doping types and concentrations and the source region comprises the first doping type with the first doping concentration.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: August 23, 2016
    Assignee: IMEC
    Inventors: Gouri Sankar Kar, Antonino Cacciato