Abstract: A semiconductor structure is provided that includes a plurality of suspended and stacked nanosheets of semiconductor channel material located above a pillar of a sacrificial III-V compound semiconductor material. Each semiconductor channel material comprises a semiconductor material that is substantially lattice matched to, but different from, the sacrificial III-V compound semiconductor material, and each suspended and stacked nanosheets of semiconductor channel material has a chevron shape. A functional gate structure can be formed around each suspended and stacked nanosheet of semiconductor channel material.

Abstract: A method is provided for manufacturing a memory. An insulating layer is formed over an array of interlayer conductors, and etched to define a first opening corresponding to a first interlayer conductor in the array, where the etching stops at a first top surface of the first interlayer conductor. A metal oxide layer is formed on the first top surface. A first layer of barrier material is deposited conformal with and contacting the metal oxide layer and surfaces of the first opening. Subsequently the insulating layer is etched to define a second opening corresponding to a second interlayer conductor in the array, where the etching stops at a second top surface of the second interlayer conductor. A second layer of barrier material is deposited conformal with and contacting the first layer of barrier material in the first opening. The first opening is filled with a conductive material.

Abstract: Described herein is a method for forming a vertical memory device (150) having a vertical channel region (113) sandwiched between a source region (109, 112) and a drain region (114). A charge trapping layer (106) is provided either side of the vertical channel region (113) and associated source and drain regions (109, 112, 114). The source region (109, 112) comprises a junction between a first region (109) comprising a first doping type with a first doping concentration and a second region (112) comprising a second doping type which is opposite to the first doping type and with a second doping concentration. The drain region (114) comprises the first doping type with a first doping concentration. In another embodiment, the drain region has two regions of differing doping types and concentrations and the source region comprises the first doping type with the first doping concentration.

Abstract: An integrated circuit includes circuitry, a first conductor coupled to the circuitry, a conductive pad coupled to the first conductor, and a second conductor coupled to the conductive pad. The second conductor would be floating but for its coupling to the conductive pad. The second conductor may be spaced apart from the first conductor by a distance that is substantially equal to a width of a merged spacer that was formed from a merging of single sidewall spacers over a conductive material from which the first and second conductors were formed.

Abstract: The present description relates to the formation source/drain structures within non-planar transistors, wherein fin spacers are removed from the non-planar transistors in order to form the source/drain structures from the non-planar transistor fins or to replace the non-planar transistor fins with appropriate materials to form the source/drain structures.

Abstract: An example image sensor includes first, second, and third micro-lenses. The first micro-lens is in a first color pixel and has a first curvature and a first height. The second micro-lens is in a second color pixel and has a second curvature and a second height. The third micro-lens is in a third color pixel and has a third curvature and a third height. The first curvature is the same as both the second curvature and the third curvature and the first height is greater than the second height and the second height is greater than the third height, such that light absorption depths for the first, second, and third color pixels are the same.

Abstract: Solid-state radiation transducer (SSRT) devices having buried contacts that are at least partially transparent and associated systems and methods are disclosed herein. An SSRT device configured in accordance with a particular embodiment can include a radiation transducer including a first semiconductor material, a second semiconductor material, and an active region between the first semiconductor material and the second semiconductor material. The SSRT device can further include first and second contacts electrically coupled to the first and second semiconductor materials, respectively. The second contact can include a plurality of buried-contact elements electrically coupled to the second semiconductor material. Individual buried-contact elements can have a transparent portion directly adjacent to the second semiconductor material. The second contact can further include a base portion extending between the buried-contact elements, such as a base portion that is least partially planar and reflective.

Abstract: One method disclosed includes, among other things, covering the top surface and a portion of the sidewalls of an initial fin structure with etch stop material, forming a sacrificial gate structure around the initial fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, removing the sacrificial gate structure, with the etch stop material in position, to thereby define a replacement gate cavity, performing at least one etching process through the replacement gate cavity to remove a portion of the semiconductor substrate material of the fin structure positioned under the replacement gate cavity that is not covered by the etch stop material so as to thereby define a final fin structure and a channel cavity positioned below the final fin structure and substantially filling the channel cavity with a stressed material.

Abstract: A method for processing a carrier may include: forming a plurality of structure elements at least one of over and in a carrier, wherein at least two adjacent structure elements of the plurality of structure elements have a first distance between each other; depositing a first layer over the plurality of structure elements having a thickness which equals the first distance between the at least two adjacent structure elements; forming at least one additional layer over the first layer, wherein the at least one additional layer covers an exposed surface of the first layer; removing a portion of the at least one additional layer to expose the first layer partially; and partially removing the first layer, wherein at least one sidewall of the at least two adjacent structure elements is partially exposed.

Abstract: An organic light-emitting display apparatus includes: a first substrate; a display unit on the first substrate, the display unit being divided into a pixel unit and a non-pixel unit located around the pixel unit; a first electrode having an island shape to correspond to the pixel unit; a second electrode facing the first electrode and over the pixel unit and the non-pixel unit; an organic light-emitting layer between the first electrode and the second electrode and to emit light toward the second electrode; a second substrate facing the second electrode and bonded with the first substrate; and a light output unit arranged as a part corresponding to the pixel unit and a light reflection unit arranged as a part corresponding to the non-pixel unit, wherein the light output unit and the light reflection unit are on an internal surface of the second substrate facing the second electrode.

Abstract: A pixel array substrate including a substrate and pixel units arranged in an array on the substrate is provided. Each pixel unit includes a TFT having a source, a gate, and a drain, a pixel electrode electrically connected to the drain, a common electrode, an insulation layer, and a test electrode. The pixel electrode is located between the common electrode and the substrate. The common electrode has slits that expose the pixel electrode. The insulation layer is located between the common electrode and the pixel electrode and has a contact hole exposing the pixel electrode. The test electrode and the common electrode belong to the same film layer, and the test electrode is separated from the common electrode. The contact hole is filled with the test electrode, and the test electrode is electrically connected to the drain. A display panel including the pixel array substrate is also provided.

Abstract: There is provided a field effect transistor having, on a substrate, at least a gate electrode, a gate insulating film, an active layer mainly containing an oxide semiconductor that contains at least one of In, Ga or Zn, a source electrode, and a drain electrode, the field effect transistor including: a heat diffusion layer, wherein, given that a thermal conductivity of the substrate is Nsub (W/mK), a thermal conductivity of the heat diffusion layer is Nkaku (W/mK), a film thickness of the heat diffusion layer is T (mm), a planar opening ratio of the heat diffusion layer is R (0?R?1), and S=T×R, the thermal conductivity Nsub of the substrate satisfies the condition Nsub<1.8, and the thermal conductivity Nkaku of the heat diffusion layer satisfies the conditions Nkaku>3.0×S^(?0.97×e^(?1.2×Nsub)) and Nkaku?Nsub.

Abstract: A method for manufacturing a transistor includes: forming a base film for supporting a catalyst for electroless plating; forming a resist layer having an opening portion corresponding to source and drain electrodes onto the base film; causing the base film within the opening portion to support the catalyst for electroless plating and performing a first electroless plating; removing the resist layer; performing a second electroless plating on a surface of an electrode which is formed by the first electroless plating and forming the source and drain electrodes; and forming a semiconductor layer in contact with surfaces of the source and drain electrodes, the surfaces facing each other, wherein an energy level difference between a work function of a material which is used for the second electroless plating and an energy level of a molecular orbital which is used for electron transfer in a material of the semiconductor layer is less than an energy level difference between a work function of a material which is us

Abstract: A semiconductor device includes a silicon substrate, an initial buffer layer disposed on the silicon substrate and including aluminum nitride (AlN), and a semiconductor device layer disposed on the initial buffer layer and including a semiconductor compound. There is no SiN between the initial buffer layer and the silicon substrate, and a silicon lattice of the silicon substrate directly contacts a lattice of the initial buffer layer.

Abstract: An object is to provide a transistor having a novel electrode structure capable of substantially maintaining on-state current while parasitic capacitance generated in an overlap portion between a source electrode layer (a drain electrode layer) and a gate electrode layer is reduced. Parasitic capacitance is reduced by using a source electrode layer and a drain electrode in a comb shape in a transistor. Curved current flowing from side edges of electrode tooth portions can be generated by controlling the width of an end of a comb-shaped electrode layer or the interval between the electrode tooth portions. This curved current compensates for a decrease in linear current due to a comb electrode shape; thus, on-state current can be kept unchanged even when parasitic capacitance is reduced.

Abstract: A semiconductor memory device is provided including first and second cell strings formed on a substrate, the first and second cell strings jointly connected to a bit line, wherein each of the first and second cell strings includes a ground selection unit, a memory cell, and first and second string selection units sequentially formed on the substrate to be connected to each other, wherein the ground selection unit is connected to a ground selection line, the memory cell is connected to a word line, the first string selection unit is connected to a first string selection line, and the second string selection unit is connected to a second string selection line, and wherein the second string selection unit of the first cell string has a channel dopant region.

Abstract: A method of forming a semiconductor device includes forming first and second semiconductor structures on a semiconductor substrate. The first semiconductor structure includes a first gate channel region having a first gate length, and the second semiconductor structure including a second gate channel region having a second gate length that is greater than the first gate length. The method further includes depositing a work function metal layer in each of a first gate void formed at the first gate channel region and a second gate void formed at the second gate channel region. The method further includes depositing a semiconductor masking layer on the work function metal layer, and simultaneously etching the silicon masking layer located at the first and second gate channel regions to re-expose the first and second gate voids. A low-resistive metal is deposited in the first and second gate voids to form low-resistive metal gate stacks.

Abstract: Devices and methods for manufacturing a device are presented. The device includes a substrate and a vertical structure disposed over the substrate. The vertical structure includes one or more memory cell stacks with a dielectric layer between every two adjacent cell stacks. Each of the one or more cell stacks includes first and second first type conductors on first and second sides of the cell stack, respectively; first and second electrodes, the first electrode adjacent the first first type conductor, the second electrode adjacent the second first type conductor; and first and second memory elements, the first memory element disposed between the first first type conductor and the first electrode, the second memory element disposed between the second first type conductor and the second electrode. The device also includes a selector element disposed over the substrate and vertically traversing through a middle portion of the vertical structure.

Abstract: Heterojunction bipolar transistors are provided that include at least one contact (e.g., collector, emitter, and/or base) formed by a heterojunction between a crystalline semiconductor material and a doped non-crystalline semiconductor material layer. An interfacial intrinsic non-crystalline semiconductor material layer is present at the heterojunction between the crystalline semiconductor material and the doped non-crystalline semiconductor material layer. The presence of the interfacial intrinsic non-crystalline semiconductor material layer improves the surface passivation of the crystalline semiconductor material by reducing the interface defect density at the heterojunction.

Abstract: A semiconductor integrated circuit device having a reservoir capacitor and a method of manufacturing the same are provided. A first insulating layer is formed on a semiconductor substrate including a first region and a second region. A first conductive layer is formed on the first insulating layer, and a second insulating layer is formed on the first conductive layer. The second insulating layer is patterned to be left in a portion of the first region. A second conductive layer is formed on the second insulating layer and the first conductive layer. The second conductive layer is etched to expose a partial surface of the first conductive layer in the first region. The second conductive layer and the first conductive layer are etched to form a reservoir capacitor in the first region and form a gate in the second region.