Abstract: In each processing device of a parallel processor system, a processor outputs a signal when all the transmit data are transmitted to a router. A latch receives the signal from the processor to output a signal set to HIGH. To an AND gate are inputted the signal set to HIGH outputted from the latch and a signal set to HIGH which indicates that the router has no receive data received from a network. The parallel processor system performs AND operation on the outputs of the AND gates of all the processing devices, and detects that a data transmit/receive processing is completed among all the processing devices according to the results of AND operation.

Abstract: An on-line processing system is provided with a plurality of work processing parts for carrying out work processes based on application programs, a plurality of buffer pools having buffer regions, a buffer control part for allocating the buffer regions of the buffer pools for use by each of the work processing parts, a threshold value control part for detecting a dangerous state of the buffer regions when the buffer control part acquires the buffer regions from the buffer pools by comparing predetermined information related to an amount of buffer regions used and a predetermined threshold value, where the dangerous state indicates a possibility of a buffer overload due to lack of storage regions provided by the buffer regions, and a work supervision control part for automatically detecting a work processing part having a priority which is lower than a predetermined priority value out of the plurality of work processing parts, and for suppressing the detected work processing part, so that the overload of the b

Abstract: A scanning unit is incorporated in a computer system communicable with another computer system for searching a random access memory unit for a message with the top priority as well as for identifying a received message with the message already stored in the random access memory unit, and a central processing unit is released from the scanning and the identification, thereby improving the throughput of given tasks.

Abstract: A program is translated by automatically generating a flowgraph, using the flowgraph to analyze the program to provide information about blocks of instructions in the flowgraph, and then using the flowgraph and the information about the blocks of instructions to generate translated instructions. Due to execution transfers to computed destination addresses that are not determined prior to program execution, it is not possible to include all of the program instructions in the flowgraph. Execution transfers to these computed destinations are coded as calls to an interpreter that interprets the untranslated code. Returns from the interpreter are made to block entry points. Moreover, information about the location of untranslated instructions in an original program is discovered during execution of a partial translation of the program, and that information is used later during re-translation of the original program.

Abstract: A blackboard parallel processing system for carrying out a general processing task using a plurality of parallel processors. In one application of the blackboard processing system, a workstation (102), which is part of an an automated workstation manufacturing system (AWMS), includes a blackboard control unit (BCU) (106) on which four separate functions are implemented in separate identical modules. The BCU includes a database module (34) having access to a global database, which is available to each of the plurality of parallel processors, referred to as knowledge source processors (KSPs) (40). A trigger module (46) includes trigger patterns that are compared to the data developed from messages transmitted by the KSPs to initiate specific tasks according to a predefined sequence. A scheduler module (42) responds to the trigger signals, by transmitting a signal to initiate each task, either by a specified KSP or by the KSP that is the least loaded with previously assigned processing task.

Abstract: A chaos processor which is able to gain a dynamic of a dynamics system and to determine whether the dynamic is gained by a random noise or by the meaningful information.

Abstract: An electronic computer cooling system having a cooling apparatus to cool an electronic computer and cooling members for thermally connecting semiconductor devices whose operating speeds are raised by cooling to a low temperature source of the cooling apparatus. Circuit boards onto which the semiconductor devices and the like constructing the electronic computer are mounted and the cooling apparatus such as a refrigerating apparatus and the like are compactly enclosed in a single casing. Or, the circuit boards and the cooling apparatus are compactly enclosed in separate detachable casings, respectively. Thus, a structure in which desired semiconductor devices can be certainly cooled by using the cooling members is obtained.

Abstract: A method and apparatus for providing picture generation and control features using a graphical data flow environment. The present invention includes a plurality of virtual instruments or VIs that can be used by themselves or in combination to create pictures that are then displayed via a picture control. Each picture VI includes a corresponding picture icon that is placed in a block diagram. Picture VIs include a unique picture data type that is used to store associated drawing instructions. A picture VI receives as an input an existing picture in the form of a picture data structure having zero or more drawing commands. The picture VI appends its respective drawing commands to the picture data structure and outputs this new data structure to subsequent picture VIs or to the picture control. The picture drawing element of the present invention is implemented as a picture control that appears on the front panel of a virtual instrument.

Abstract: A Serial Video Processor (SVP) is provided for processing data through a plurality of parallel processing elements (228). Data is first stored in a data input register (DIR) (222) and then processed through the PE (228). The data is then output into a Data Output Register (DOR) (230). During one pass of data through the PE (228), a variable is calculated and stored in an auxiliary register (242). This auxiliary value is typically selected from one of the processing elements representing a value over the entire or part of the input vector of data. A multiplexer (248) selects this value from the output value stored in the register (242) and then inputs it to a second multiplexer (240). The second multiplexer (240) is operable to select either a predefined variable from either another auxiliary register (238) or from an instruction generator ROM (236), or select the precalculated variable stored in the register (242).

Abstract: An occurrence capability which allows a first function to "go to sleep" while waiting for a second function to produce a result. In this manner, the first function does not consume any CPU time while waiting for the second function. Three icons are provided with associated control software which implement the occurrence function. A Wait on Occurrence function icon is associated with the first function that is waiting on the result from the second function. A Set Occurrence function icon is typically associated with the second function icon and triggers an occurrence when the second function produces the desired result. A Generate Occurrence function icon is used to pass identifier values linking multiple sources and destinations having Set Occurrence and Wait on Occurrence function icons, respectively.

Abstract: A high byte right-shift detection mechanism with a register alias table unit (RAT) for selectively causing right-shifting of high byte physical source register data before operations are executed within a microprocessor is described. A high byte right-shift condition occurs when a logical source register that is presented to the RAT for renaming is a high byte register and the corresponding physical source register selected by the RAT is not right-adjusted. A non right-adjusted physical source register is detected when either the physical source register is an architectural state register or the physical source register is a larger width register that includes the renamed high byte register.

Abstract: An automatic support tool generating system includes a knowledge acquisition tool for acquiring knowledge from answers received in response to questions generated by the knowledge acquisition tool, and a database for storing the knowledge acquired by the knowledge acquisition tool as data and for forming a knowledge data group, where the knowledge acquisition tool acquires, based on attribute data which are obtained as the answers, a design support knowledge data group used for generating a design support tool which is necessary to make a desired design.

Abstract: A system for enabling a central location to control a service at a plurality of remote locations. The system includes a plurality of control modules for controlling the length of time for actuation of a switch at remote locations. A magnetic stripe card programs one of the plurality control modules to provide a service to the remote location for a predetermined period of time. The magnetic stripe card also programs the remote control module with a series of progressive warning modes. A central site manager programs the magnetic stripe cards for use with a specific control module. The central site manager contains a storage means containing information concerning each control module under the control of the site manager and information concerning all of the magnetic stripe cards issued by the central site manager.

Abstract: A method and apparatus for executing control flow instructions in a computer system is described. The present invention includes a method and apparatus for decoding multiple instructions. The instructions decoded include control flow instructions and arithmetic instructions. The present invention also includes a method and apparatus for executing the decoded control flow instructions. The present invention as includes a method and apparatus for executing the decoded arithmetic instructions. In the currently preferred embodiment, the control flow instructions and the arithmetic instructions are executed in parallel.

Abstract: A plurality of data packets flow into a data driven type information processor when a program is executed. These data packets each queue for a data packet to be paired therewith in a matching memory in the information processor. Among these data packets, data packets which store instruction information executable in parallel are designated to have different address spaces in the matching memory for queuing data packets to be paired therewith, and therefore collision due to competition in accessing on the matching memory is avoided, thereby increasing processing speed.

Abstract: A data editing apparatus includes a mass storage device to edit multimedia data such as picture, audio, text and other data. By the visual graphic display of the time positions of the edited information, the user can easily grasp the reproduction time of the picture, text and audio data, thereby simplifying synchronization of plural media data. Graphic editing may be effected to facilitate multimedia data editing.

Abstract: An apparatus and method for generating a topology map representing the physical connectivity between devices on an FDDI network. A network management station constructs a connectivity table by first selecting a port which feeds a medium access controller (medium access controller) and whose external connectivity is unknown. The network management station then determines the upstream neighbor medium access controller of the medium access controller fed by the selected port. The network management station then determines the port which is fed by the output of the upstream neighbor medium access controller. The network management station then enters data into the table indicating an external connection between the selected port and the port which is fed by the output of the upstream neighbor medium access controller.

Abstract: An autoprobe feature which illustrates the data output of each node as data propagates through a data flow program. As each node in the diagram executes or fires, a routine is invoked which displays the resultant data on the block diagram. Thus, a user can select the autoprobe feature and visually see the data flow out each node as the block diagram executes. Thus, the user can immediately determine if one node is providing incorrect output.

Abstract: A system and method for providing attribute nodes in a data flow diagram which allow a user to programmatically access various parameters of a control or indicator. In this manner, a user can programmatically make changes that affect the output or appearance of controls and indicators. A user can also access these parameters interactively during execution of a block diagram. A user can creates an attribute node containing one or more attributes corresponding to controls that affect a parameter of the control, such as the color used for the respective display, the visibility of the control, the scales or cursor position for respective graphs or charts, etc. The purpose of an attribute node is to affect the visual output of a control provided on the front panel depending on events which occur during execution of a VI or on user input during execution of a VI.

Abstract: A microprocessor having a test mode wherein a test instruction including an instruction for executing the whole microprogram routine and a step-execution instruction for executing only one microinstruction of an arbitrary address in a micro ROM for easily diagnosing each internal function blocks by independently operating them, and a circuit for changing the content of sequence field of the microinstruction outputted to the microsequencer at executing the step-instruction. The circuit is used for executing the microprogram routine step by step with combining instructions which execute only one microinstruction, or a specified instruction between two continuous microinstructions of a microprogram routine, so that the cause of fault points in the microprocessor can be easily specified.