Abstract: The relative location of a first device is detected with respect to a second device on a network. The second device is instructed to listen for messages from the first device. When the second device receives a first message from the first device, the second device records a first port of the second device over which the second device received the first message. Optionally, the second device also records an indication that the second device received a message from the first device over a single port. When the second device receives an additional message from the first device over a port of the second device other than the first port of the second device, the recording of the first port is invalidated. This is done, for example by changing the indication that the second device received the message from the first device over a single port, to an indication that the second device received messages from the first device over multiple ports.

Abstract: A processing system includes memory page selection of multiple memory pages in an interrupt environment. The processing system includes a processor and memory page selection control for selecting one memory page responsive to a first address generated by the processor and another memory page responsive to a second address generated by the processor. The memory page selection control includes a page latch which can be overridden by an interrupt to permit the processor to service an interrupt from one of the pages but which returns the processor to the memory page from which it was fetching program instructions at the time of the interrupt. To coordinate page selection, the processor executes program instructions from dedicated paging instructions including interface modules, decode modules, and transition modules stored in each page which are configured to assure smooth page transitions and efficient interrupt servicing.

Abstract: A graphical system for executing a process or for programming a computer to execute the process is based on graphical programming techniques. Techniques include composing a graphical front panel of an instrument which provides a means for the user to provide input and monitor outputs of the process, composing a data flow diagram using graphical representations of data flow structures, and in response to the data flow diagram and the panel diagram, composing a sequence of execution instructions to carry out the diagrammed process in response to inputs provided by the panel to supply outputs displayed by the panel. The system is based on libraries of executable functions and variable types having corrresponding icons. The user selects icons which have corresponding entries in the libraries to assemble the diagrams.

Abstract: A relatively fast system control processor, such as an Intel 8051, is substituted for an Intel 8042 microprocessor in a PC/AT type compatible personal computer. In one embodiment of the invention, a System Control Processor Interface (SCPI) is provided between the central processing unit (CPU) and the system control processor (SCP) to maintain compatibility with the PC/AT bus. The combination of the faster SCP and the SCPI interface improves the overall system performance. Control circuitry is also provided for setting the A20 signal relatively quickly to allow memory access above one megabyte. In an alternate embodiment of the invention, a Mouse Keyboard Interface (MKI) is provided. The MKI provides even quicker switching of the Gate A20 signal by eliminating the need to interrupt the SCP. The MKI also provides support for a type PS/2 mouse.

Abstract: A data processing system includes a processor coupled to a system bus. A memory controller is also coupled to the system bus and to a memory bus in communication with a plurality of single in-line memory modules (SIMMs). Each SIMM comprises a plurality of DRAMS coupled to four cross bar switches (CBSs), such that address and data information is provided to the DRAMs through the cross bar switches. Each CBS includes a counter and decoder which controls a multiplexor. The multiplexor is coupled to enable ID logic, and four input registers (A.sub.R, B.sub.R, C.sub.R, D.sub.R), such that register A.sub.R is coupled to the output of the multiplexor, and the remaining registers are coupled to the input side of the multiplexor. An input buffer on the CBS is coupled to four input registers (A'.sub.W, B'.sub.W, C'.sub.W, D.sub.W). In addition, three of the input registers (A'.sub.W, B'.sub.W, C'.sub.W) are coupled to intermediate input registers A.sub.W, B.sub.W and C.sub.W.

Abstract: A plurality of processors form a network used to communicate with one or more peripheral devices and the system control processor. One processor is dedicated to at least one peripheral device. Since the system control processor is not burdened with the relatively slow communications protocol with the peripheral devices, it is free to do other tasks which improves the overall system performance. Communication protocol between the dedicated processors allows for local and global communication.

Abstract: The invention establishes the context in which data exchanged between dissimilar relational database management systems can be mutually understood and preserved. The invention accomplishes this by establishing layers of descriptive information which isolate machine characteristics, levels of support software, and user data descriptions. Optimized processing is achieved by processing the different descriptor levels at different times during the development and execution of the database management systems. Minimal descriptive information is exchanged between the cooperating database management systems. For systems which match, data conversion is completely avoided. For systems which do not match, data conversion is minimized.

Abstract: Apparatus for implementing input/output (I/O) operations in a computer system operating under the control of a UNIX* operating system includes a dedicated communications processor in addition to the main or host processor. These two processors communicate via a shared memory which may be independently accessed by each processor. The functions performed by the terminal I/O driver and the line discipline modules are divided between the host and communications processors. The communications processor performs all canonical processing of the data received from the terminal I/O devices. It also maintains a data structure that indicates the instantaneous status of each terminal I/O device. Using this data structure, the communications processor is able to operate in a substantially interrupt-free environment, polling only those I/O devices that are indicated, in the status data structure, as needing service. A message facility in the shared memory controls communication between the processors.

Abstract: A method and apparatus for storing and rewriting programs in an IC card. The system provides for storing programs in subdivided portions identified by attribute information including a program number, size and address. The system enables the rewriting of constituent elements of programs without the need for rewriting larger portions. The information identifying the programs parts is stored in an attribute information table in which said sub-area discrimination information and said management information are stored in combination.

Abstract: A method and apparatus for implementing a capture of a long contiguous chain of data bus cycles for the memory system of a data processing system with memory units that alternate between real time capture of segments of the chain of data bus cycles and processing of the data bus signals in the captured segments.

Abstract: A process of compiling using a vectorized checkup method for converting array calculations appearing in a loop to be vectorized in a source program into vector calculations. The process determines a number of dimensions of an array calculation within a loop and performs a dependence analytical process.

Abstract: A device providing pointing device functions in a keyboard without requiring the keyboard operator to remove any fingertip from the keys. A computer keyboard keyswitch mounting plate is supported for horizontal displacement against a resistive force. A transducer for measuring the force exerted in the plane of the keyboard key tops is attached between the keyboard case and the keyswitch mounting plate. The direction and magnitude of the force can be measured and encoded so they may be used to emulate the signals generated by a pointing device. The operator may elect a pointing device mode by merely applying sufficient force along the plane of the surface of the key tops, thus switching from a keyboard mode to a pointing device mode, without moving the fingers from a typing position.

Abstract: A method of conveniently making a selection from a set of options available in a computer program is described. As successive letters which make up the proposed selection are entered, successively smaller lists of options corresponding to the entered letters are displayed. At any point, the user makes a selection by moving a cursor to a desired selection and pressing a button or key to indicate that the selection has been made.

Abstract: A shared power controller for a rack of interface devices which are shared among a plurality of processor units. The shared power controller may be commanded into a power up mode by any connected central processor via its system power interface. A power down of a connected rack of interface units may, however, only be effected when all the connected CPU units enter a power down mode. A system power controller provides both remote and local operation such that diagnosis and analysis of problems may be effected locally at each rack of input/output devices.

Abstract: A computer system for building models of complex business transactions in an information management system. The system includes storage means for storing ordered sets of references to design data, such as entities. The ordered sets, or entity-sets, are assigned a value, and may then be manipulated in a manner similar to a data variable. The references may be ordered in accordance with predetermined criteria, or operator selected criteria.

Abstract: A data processing apparatus includes an instruction issuing unit, an interval holding unit, a passing control unit, and a nullification processing unit. The instruction issuing unit tentatively issues a vector store instruction having no definitive data as an instruction not subjected to actual vector store processing. The interval holding unit obtains and holds a store interval block address to be operated by the vector store instruction tentatively issued from the instruction issuing unit. The passing control unit compares a block address indicated by a scalar load/store instruction issued from the instruction issuing unit with the store interval block address held by the interval holding unit. If the block address falls within the range of the store interval block addresses, the passing control unit causes processing for the scalar load/store instruction to wait until the vector store instruction is finally issued from the instruction issuing unit and processed.

Abstract: An adaptive segment control for controlling performance of a multi-segment cache in a storage system. The adaptive segment control segments the cache to operate at a selected working segmentation level. A plurality of virtual cache tables are segmented such that one table operates at the working segmentation level and the other tables operate at different segmentation levels. During operation, the adaptive segment control monitors memory instructions transmitted by a host computer to the storage system and stores the instructions in an instruction queue. While the storage system is in an idle state, the adaptive segment control performs hit ratio simulations on the virtual cache tables by executing a selected number of instructions stored in the instruction queue. The working segmentation level is adjusted to equal the segmentation level of the virtual cache table having the highest hit ratio.

Abstract: A multiple file system having multiple identical file units each holding the same data files identified by a chronological revision number. Each file unit, in addition to magnetic data storage, contains input receiver and output driver stages which can be inhibited by a prohibition signal generated by a latch relay circuit in a corresponding file unit to keep the other file unit inactive when a failure occurs in the other file unit. Upon return of the other file to normalcy, the corresponding file is reset to discontinue the prohibition signal and the revision numbers of corresponding files in each file unit are compared to replace the file contents having the older revision number with the file contents having the newer revision number.

Abstract: A language structure and translator specifically adapted for use in constructing computer programs for controlling chemical and physical processing. The translator converts to compilable code programs written as statements expressing control intentions or results. Each textual function and statement is expressed as a data structure which expresses the function, as configured, and the state and values most recently calculated for the relevant variables. Provision is made for treating the program structure (i.e., control connections, program order and components, etc.) as a part of the dynamic state of the application. Graphical symbols, or icons, are employed to draw the eye to critical features in the control program and to lead the eye through critical interrelationships among the several commands of a complicated control system. At the same time, the translator treats the keystrokes generating these icons as statements (i.e.

Abstract: A computer system for creating and manipulating subsets of dynamic information systems models of organizations. Generally, the system includes a plurality of dynamicallly linked modelers. The system includes a filter for creating a subset of a model. Each model subset is defined by operator-determined selection criteria. The subset is created by applying the selection criteria to the design data set of the model to be filtered. The resulting model subset may be displayed in a graphical representation. Such representations may enable the user to dynamically interact with the system.