Abstract: A semiconductor device includes a transistor in a semiconductor substrate. The transistor includes a drift zone of a first conductivity type adjacent to a drain region, and a first field plate and a second field plate adjacent to the drift zone. The second field plate is arranged between the first field plate and the drain region. The second field plate is electrically connected to a contact portion arranged in the drift zone. The transistor further includes an intermediate portion of the first conductivity type at a lower doping concentration than the drift zone. A distance between the intermediate portion and the drain region is smaller than the distance between the contact portion and the drain region.

Abstract: Embodiments are directed to devices and methods for integrating laterally diffused metal oxide semiconductor (LDMOS) technology on vertical field effect transistor (VFET) technology, which enables VFET applications to be broadened to include power amplifiers. By providing a combined asymmetric underlapped drain, high current, low subthreshold slope and LDMOS lightly doped drain, high drain resistance and high drain voltage are enabled.

Abstract: The present invention is a bonded body in which an aluminum member constituted by an aluminum alloy, and a metal member constituted by copper, nickel, or silver are bonded to each other. The aluminum member is constituted by an aluminum alloy in which a solidus temperature is set to be less than a eutectic temperature of a metal element that constitutes the metal member and aluminum. A Ti layer is formed at a bonding portion between the aluminum member and the metal member, and the aluminum member and the Ti layer, and the Ti layer and the metal member are respectively subjected to solid-phase diffusion bonding.

Abstract: Embodiments of the present disclosure provide techniques and configurations for a semiconductor package with thermal fins, in accordance with some embodiments. In embodiments, a package assembly includes a die and a mold compound disposed on the die, to encapsulate the die. The package may further include a thermal solution including one or more thermal fins attached to the mold compound at their respective ends. The thermal fins may be disposed substantially flat on a top surface of the mold compound at a first temperature, and rise away from the top surface of the mold compound in response to a change of temperature to a second temperature, to reach an enclosure that surrounds the package assembly, to provide direct heat conductivity between the die and the enclosure. The second temperature may be greater than the first temperature. Other embodiments may be described and/or claimed.

Abstract: The present invention disclosed a micro acoustic collector and CMOS microphone single chip. The micro acoustic collector comprising: a plurality of leaf-shaped structures annularly arranged with symmetry, each of the plurality of leaf-shaped structure having a suspended arm and a restrained arm, and the suspended arm of the plurality of leaf-shaped structures connected to a suspended fulcrum, and a plurality of through-vias formed in the suspended fulcrum and the plurality of leaf-shaped structures; a plurality of support pillars uniformly disposed under edges of the plurality of leaf-shaped structures corresponding to the restrained arms and the suspend arms; and a base metal layer formed under and insulated from the plurality of support pillars, and facing towards the inner-annular-supported acoustic collection film to form a hollow space.

Abstract: The present invention disclosed a micro acoustic collector with a lateral cavity, comprising: a base metal layer; a movable film, an annular side wall; a lateral metal layer. The movable film faces towards the base metal layer to form a hollow space. The lateral metal layer is formed at a side of the movable film and around the movable film, fixed by the annular side wall and spaced apart from peripheral of the movable film by a distance, and the lateral metal layer faces towards the base metal layer to form a lateral cavity to assist an acoustic collection.

Abstract: A method is provided for fabricating a FinFET. The method includes providing a substrate including an NMOS region; forming a plurality of fins on the substrate; forming an isolation layer between adjacent fins and on the substrate; forming a gate structure across a length portion of the fin; forming a first mask layer on the top surface and sidewalls of the fin; etching the first mask layer to expose the top surface of the fin on both sides of the gate structure; removing a thickness portion of the fin on both sides of the gate structure, wherein the etched fin and the remaining first mask layer form a first trench; performing a thinning treatment of the remaining first mask layer on a sidewall of the first trench to increase width of the first trench; and forming an N-type in-situ doped epitaxial layer to fill up the first trench.

Abstract: A reactive material erasure element including a reactive material is located between PCM cells and is in close proximity to the PCM cells. The reaction of the reactive material is trigger by a current applied by a bottom electrode which has a small contact area with the reactive material erasure element, thereby providing a high current density in the reactive material erasure element to ignite the reaction of the reactive material. Due to the close proximity of the PCM cells and the reactive material erasure element, the heat generated from the reaction of the reactive material can be effectively directed to the PCM cells to cause phase transformation of phase change material elements in the PCM cells, which in turn erases data stored in the PCM cells.

Abstract: A semiconductor structure includes a plurality of pairs of nonvolatile memory cells arranged in a row, an edge cell positioned adjacent to the pairs of nonvolatile memory cells, and first, second, third, and fourth gates. Each pair of nonvolatile memory cells includes first and second nonvolatile memory cells. The first and second gates extend across the first nonvolatile memory cells, the second gate partially overlapping the first gate, and the third and fourth gates extend across the second nonvolatile memory cells, the fourth gate partially overlapping the third gate. Each of the first, second, third, and fourth gates has an end portion that is positioned in the edge cell, and the edge cell includes a protection layer that is positioned over the end portions of the first, second, third, and fourth gates and covers an end face of the second and fourth gates.

Abstract: A graphene display is provided. The graphene display includes a first graphene light-emitting unit and a second graphene light-emitting unit, which are stacked and overlapped, and a metal shield layer disposed between the first graphene light-emitting unit and the second graphene light-emitting unit. The graphene display is simple in structure, and the colors of the emitted light at the two sides will not change because of the electric field of the gate electrode pattern so as to have more stable color and color reproduction.

Abstract: A device includes a semiconductor substrate, and a Device Isolation (DI) region extending from a top surface of the semiconductor substrate into the semiconductor substrate. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the DI region. A gate electrode is disposed over the gate dielectric, wherein a notch of the gate electrode overlaps a portion of the DI region.

Abstract: A semiconductor device having favorable reliability which is capable of retaining data for a long time is provided. The semiconductor device includes a first gate electrode, a first gate insulator over the first gate electrode, a first oxide over the first gate insulator, a second oxide and a third oxide over the first oxide, a first conductor over the second oxide, a second conductor over the third oxide, a fourth oxide over the first oxide, the first conductor, and the second conductor, a second gate insulator over the fourth oxide, and a second gate electrode over the second gate insulator. The first conductor is in contact with a top surface of the second oxide, a side surface of the second oxide that faces the third oxide, and part of a top surface of the first oxide. The second conductor is in contact with a top surface of the third oxide, a side surface of the third oxide that faces the second oxide, and part of the top surface of the first oxide.

Abstract: Herein disclosed a display apparatus including: a pixel array having a matrix of pixel circuits each including respective electrooptical elements for determining a display brightness level and respective drive circuits for driving the electrooptical elements; wherein adjacent two of the pixel circuits are paired with each other, and each of the drive circuits of the adjacent two pixel circuits includes at least one transistor having a low-concentration source/drain region or an offset region of an offset gate structure, the electrooptical elements and the drive circuits of the adjacent two pixel circuits being laid out such that a line interconnecting a drain region and a source region of the at least one transistor extends parallel to a direction of pixel columns of the pixel circuits of the pixel array.

Abstract: Embodiments are directed to a method for forming a semiconductor structure by depositing a stack of alternating layers of two materials over a substrate and defining field-effect transistor (FET) and diode regions. The method further includes depositing a mask, where the mask covers only the FET region while leaving the diode region uncovered. The method further includes doping the material in the diode region with a dopant, implanting epitaxial material with another dopant to form PN junctions, stripping the mask from the structure, forming a metal gate conductor over the FET region, and depositing a metal over the substrate to create terminals.

Abstract: An area occupied by a circuit element having at least a capacitor and a transistor is reduced in a semiconductor device. In a semiconductor device including a first transistor, a second transistor, and a capacitor, the first transistor and the capacitor are provided over the second transistor. Then, a common electrode, which serves as one of a source and a drain of the first transistor and one electrode of the capacitor, is provided. In addition, the other electrode of the capacitor is provided over the common electrode.

Abstract: A fin field effect transistor and method of forming the same. The fin field effect transistor includes a semiconductor substrate having a fin structure and between two trenches with top portions and bottom portions. The fin field effect transistor further includes shallow trench isolations formed in the bottom portions of the trenches and a gate electrode over the fin structure and the shallow trench isolation, wherein the gate electrode is substantially perpendicular to the fin structure. The fin field effect transistor further includes a gate dielectric layer along sidewalls of the fin structure and source/drain electrode formed in the fin structure.

Abstract: According to one embodiment, the insulating layer is provided on the terrace portions. The plurality of contact portions extend through the insulating layer in the stacking direction and contact the terrace portions. The second columnar portion extends through the insulating layer and through the second stacked portion in the stacking direction, and includes a second semiconductor body contacting the first semiconductor region. The first insulating portion divides the first semiconductor region in the first direction. The first insulating portion is provided under a boundary portion between the first stacked portion and the second stacked portion.

Abstract: Some embodiments include an assembly having pillars of semiconductor material arranged in rows extending along a first direction. The rows include spacing regions between the pillars. The rows are spaced from one another by gap regions. Two conductive structures are within each of the gap regions and are spaced apart from one another by a separating region. The separating region has a floor section with an undulating surface that extends across semiconductor segments and insulative segments. The semiconductor segments have upper surfaces which are above upper surfaces of the insulative segments; Transistors include channel regions within the pillars of semiconductor material, and include gates within the conductive structures. Some embodiments include methods for forming integrated circuitry.

Abstract: A light emitting device includes a substrate including an entire top surface that is flat; a light emitting diode on the substrate; a lead frame formed on the flat top surface of the substrate, the lead frame electrically connected to the light emitting diode; a dam member disposed on the lead frame and being adjacent to the light emitting diode, the dam member having a circular configuration which has an opening; a first member disposed on the light emitting diode, the first member including a fluorescent substance to convert a light emission spectrum of light from the light emitting diode; a second member disposed in the opening of the dam member, a circumference of the second member being defined by the dam member and contacting an inner vertical side surface of the dam member, wherein the second member excludes the fluorescent substance; and a lens disposed on the second member.

Abstract: A magnetic cell includes a magnetic region formed from a precursor magnetic material. The precursor magnetic material included a diffusible species and at least one other species. An oxide region is disposed between the magnetic region and another magnetic region, and an amorphous region is proximate to the magnetic region. The amorphous region includes an attracter material that has a chemical affinity for the diffusible species that is higher than a chemical affinity of the at least one other species for the diffusible species. Thus, the diffusible species is transferred from the precursor magnetic material to the attracter material, forming a depleted magnetic material. The removal of the diffusible species and the amorphous nature of the region of the attracter material promotes crystallization of the depleted magnetic material, which enables high tunnel magnetoresistance and high magnetic anisotropy strength. Methods of fabrication and semiconductor devices are also disclosed.