Patents Examined by Melvin B. Chapnick
  • Patent number: 4296466
    Abstract: A data processing system having a host processor, a host memory, a host memory management unit and an input/output bus and further including a separate input/output (I/O) processor with its own local memory for handling the transfer of data between I/O devices on its own I/O processor I/O bus and the host main memory. The I/O processor has the capability of directly accessing main memory via the host standard data channel. The I/O processor has the capability of interrupting the host processor operation in a special way by a "micro-interrupt" process such that the host processor thereby re-allocates the contents of a selected memory allocation unit (MAP) of the host memory management unit faster than using standard interrupt routines.
    Type: Grant
    Filed: January 23, 1978
    Date of Patent: October 20, 1981
    Assignee: Data General Corporation
    Inventors: James M. Guyer, Joseph T. West
  • Patent number: 4291370
    Abstract: An interface circuit for coupling a digital processor to a core memory. The interface circuit accepts as inputs address signals, data signals, and control signals from the processor and output date from the core memory. The output of the interface circuit consists of control signals to control the memory and a parallel digital data word having 2N bits where N is the number of parallel bits transferred by the digital processor during the execution of an instruction to transfer data to or input data from an external device. To store a digital data word in a particular location in the core memory, the digital processor first transfers a digital data word having N bits to a buffer memory which is a part of the interface circuit. Next, the digital processor executes a store in memory instruction.
    Type: Grant
    Filed: August 23, 1978
    Date of Patent: September 22, 1981
    Assignee: Westinghouse Electric Corp.
    Inventor: Larry L. Charles
  • Patent number: 4287558
    Abstract: A system for processing data received in the form of sample pulses has a memory with first and second major memory areas. A buffer register stores data temporarily to enable an interface between the timing of the system and of a sampled analog signal. A central processor processes data stored in one major memory area while data stored in the other major memory area is being transferred between the memory and the buffer register. The data transfer occurs during time periods while the central processor does not have access to the memory. One data item is outputted for each sample pulse received. This way, the cycle time of the sample pulses may be much greater than the cycle time of the central processor.
    Type: Grant
    Filed: September 21, 1978
    Date of Patent: September 1, 1981
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Takao Nishitani
  • Patent number: 4279016
    Abstract: An interrupt system for an instruction pre-fetch microprocessor is provided. The interrupt system includes an instruction address register coupled to a storage address register for holding the next succeeding instruction address to the pre-fetched in a sequence of instructions. A storage address register is provided and is coupled to the instruction address register and is coupled to the storage address register for holding the storage address to be accessed. A first latch receives and stores an interrupt request from one of a plurality of peripheral devices. A second latch, enabling interrupts, is coupled to the storage unit and controlled by instructions from the microprocessor. An interrupt link register stores values of the instruction address register and page information together with arithmetic and logic unit status bits when an interrupt request has occurred from one of the plurality of peripheral devices and an interrupt cycle is executed.
    Type: Grant
    Filed: June 21, 1979
    Date of Patent: July 14, 1981
    Assignee: International Business Machines Corporation
    Inventors: Joel C. Leininger, Floyd R. Bliss, Peter T. Fairchild
  • Patent number: 4276594
    Abstract: A digital computer with the capability of incorporating multiple central processing units (CPU's), utilizes an address and data bus between each central processing unit and from one to fifteen intelligent composite memory and input/output modules (MIO). Data is transferred to and from each MIO and the CPU synchronously by a bus during one phase of a three phase clocking cycle. During a second phase of the clocking cycle data on one or more low speed serial data channels within each MIO is transferred to and from the MIO and external devices. During the third phase of the clocking cycle data on a high speed direct memory access channel (DMA) is transferred to and from the MIO and one or more external devices. Additional CPU's can be interconnected with the first CPU by means of an inter-processor buffer module (IPB) which interconnects to the bus at one end and the additional CPU, by means of a bus, at its other end.
    Type: Grant
    Filed: June 16, 1978
    Date of Patent: June 30, 1981
    Assignee: Gould Inc. Modicon Division
    Inventor: Richard E. Morley
  • Patent number: 4272829
    Abstract: A register circuit capable of use in various components of a computer. The register circuit includes two registers and logic circuitry that enables plural data buses to be selectively connected in various configurations to the data inputs and outputs of the registers. In an embodiment showing the register circuit constructed using emitter coupled logic, a clocking circuit generates clocking signals for selecting the data buses to be connected to the input of each register. Each register comprises plural master-slave flip-flops which receive the clocking signals from the clocking circuit and operatively connect the flip-flops to the selected bus or buses in response to such signals.
    Type: Grant
    Filed: December 29, 1977
    Date of Patent: June 9, 1981
    Assignee: NCR Corporation
    Inventors: Carson T. Schmidt, William P. Ward, Rocky M. Y. Young
  • Patent number: 4272810
    Abstract: A message storage system (104) deletes trailing silence from messages stored therein. Voice messages are converted to digital signals and stored as data blocks in a digital storage system (114a). Voice signals are detected in messages to be stored and voice present bits are generated and included in the individual data blocks to indicate whether voice signals are present in the data blocks. During storage of the data blocks, the voice present bits which identify data blocks containing no voice signals increment a counter (311), and voice present bits which identify data blocks containing voice signals clear the counter (311). The final count in the counter is representative of the trailing data blocks which do not contain voice signals, i.e., silence, and these data blocks are deleted from the digital storage system.
    Type: Grant
    Filed: December 21, 1978
    Date of Patent: June 9, 1981
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Geoffrey W. Gates, Garry D. Kepley
  • Patent number: 4271484
    Abstract: Signals representing the past and present states of a condition under test during an instruction execution cycle, as well as a signal indicating that an execute cycle has taken place, are utilized as address signals applied to a memory which feeds an output to control a bistable element. The bistable element is set to the state of the memory output signal and supplies the address signal indicative of the past state of the condition under test. The memory is coded to respond at its output with signals controlling the bistable element such that once a given state of the condition under test is detected and stored in the bistable element, the latter is inhibited from switching regardless of any further changes in the condition under test during the current instruction execution cycle.
    Type: Grant
    Filed: January 3, 1979
    Date of Patent: June 2, 1981
    Assignee: Honeywell Information Systems Inc.
    Inventors: Arthur Peters, Virendra S. Negi
  • Patent number: 4271465
    Abstract: A plurality of information handling units communicate asynchronously via a common bus using a single signal line. Each information handling unit includes a self-control type bus utilization unit connected to the signal line and operative to connect the common bus to an internal bus of the information handling unit. This unit includes an own name address generator responsive to a bus request signal for outputting the address of the information handling unit, the address being encoded according to that information handling unit's priority among the plurality of information handling units. Transmission gates couple the address to the common bus, and a decision unit compares a signal on the common bus and the address to make a decision based on the assigned priority of the information handling unit to derive a bus grant signal. This signal and a bus available signal on the single signal line are used to derive a signal to drive transmission gates that couple the common bus to the internal bus.
    Type: Grant
    Filed: October 3, 1978
    Date of Patent: June 2, 1981
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Toshinori Ohtsuka, Takashi Toyohuku
  • Patent number: 4271466
    Abstract: A direct memory access control (DMAC) system, in a data processing system, includes at least a central processing unit and a memory, the memory being capable of storing and providing data in any one of several predetermined formats. A plurality of input/output control ports, each connecting a respective input/output device to a common data bus, control data transfer in either direction between the device and the memory. A direct memory access control unit is connected to the common data bus for receiving an access request signal from any of the plurality of input/output control ports, and is connected to the memory for providing thereto, in response to the access request signal, instructions at least as to the size and desired format of the data transfer. A bus switching unit connects the common data bus to the memory, and is connected to the direct memory access control unit for receiving the instructions.
    Type: Grant
    Filed: November 21, 1978
    Date of Patent: June 2, 1981
    Assignee: Panafacom Limited
    Inventors: Mitsuru Yamamoto, Jun Arai, Takao Isogawa, Isamu Hasebe
  • Patent number: 4271464
    Abstract: In order to provide an interrupt command signal in a computer and receive an interrupt acknowledgment at a single input/output terminal, an interrupt command encoder includes an inverter for receiving an interrupt command at a first logic level and providing the interrupt command at a second logic level to the single input/output terminal. An interrupt command logic circuit responds to the interrupt command to produce an interrupt signal to the computer which, in turn, is fed back to the single input/output terminal as an interrupt acknowledgment signal of the first logic level. A gate connected to the interrupt command input and to the single input/output terminal is responsive to the interrupt acknowledgment signal of the first logic level only to provide a corresponding signal acknowledging that the computer has received the interrupt signal.
    Type: Grant
    Filed: September 29, 1978
    Date of Patent: June 2, 1981
    Assignee: Siemens Aktiengesellschaft
    Inventor: Richard W. MacMillan
  • Patent number: 4270184
    Abstract: A programmable logic controller with an input-output device for applying data indicating the status of external devices and controlling the devices. A main memory is provided for storing universal instructions and sequence instructions. An arithmetic operation control unit connected to the main memory repeatedly executes the universal and sequence instructions. A switch is provided for connecting the arithmetic operation control unit to a first read-only memory device for storing microinstructions used for executing universal instructions and to a second read-only memory device for storing microprograms used for executing sequence instructions. The switch provides arithmetic control over the sequence instructions microprogram and the universal instructions microprogram. The arithmetic operation control unit and a sequence control unit together execute sequence instructions in response from the microprogram instructions stored in the second read-only memory device.
    Type: Grant
    Filed: March 16, 1978
    Date of Patent: May 26, 1981
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Yoshiyuki Shimokawa
  • Patent number: 4268901
    Abstract: A variable configuration accounting machine having a central processor unit (CPU) of an LSI (Large Scale Integration) microprocessor type and a plurality of peripheral units selectively connectable to the CPU which gives a selected configuration to the machine. The CPU is connected to a pair of memories. The first memory stores instructions and data, and the second memory stores microprograms. The capacity of both memories is variable according to the number and type of the peripheral units connected to the CPU for a given configuration of the machine. In the second memory is permanently stored an initialization microprogram that, when activated by the operator, automatically causes the identification by the CPU of the number and type of peripheral units connected to the CPU.
    Type: Grant
    Filed: August 21, 1975
    Date of Patent: May 19, 1981
    Assignee: Ing. C. Olivetti & C., S.p.A.
    Inventors: Angelo Subrizi, Ettore Violino
  • Patent number: 4268907
    Abstract: A cache unit includes a cache store organized into a number of levels to provide a fast access to instructions and data words. Directory circuits, associated with the cache store, contain address information identifying those instructions and data words stored in the cache store. The cache unit has at least one instruction register for storing address and level signals for specifying the location of the next instruction to be fetched and transferred to the processing unit. Replacement circuits are included which, during normal operation, assign cache locations sequentially for replacing old information with new information. The cache unit further includes apparatus operative in response to a first predetermined type of command specifying the fetching of data words to set an indicator flag to a predetermined state.
    Type: Grant
    Filed: January 22, 1979
    Date of Patent: May 19, 1981
    Assignee: Honeywell Information Systems Inc.
    Inventors: Marion G. Porter, Robert W. Norman, Jr., Richard T. Flynn
  • Patent number: 4266281
    Abstract: A programmable controller includes a processor formed around a pair of four-bit bipolar microprocessors. A control program formed by selected macroinstructions is stored in a random access memory and it is executed by sequentially mapping each macroinstruction operation code into a corresponding microroutine which is stored in a read-only memory. Some macroinstructions include operand addresses of a line in an I/O image and data table portion of the random access memory, and one macroinstruction (ADX) expands this operand address to enable the I/O image and data table to be expanded in size. A timer macroinstruction is executed in part by reading the state of a counter which is driven by a real time clock, and arithmetic functions are performed with the use of a decimal adjust accumulator.
    Type: Grant
    Filed: April 2, 1979
    Date of Patent: May 5, 1981
    Assignee: Allen-Bradley Company
    Inventors: Odo J. Struger, Ernst H. Dummermuth
  • Patent number: 4263650
    Abstract: A digital system including a plurality of metal-oxide-semiconductor (MOS) chip random access memories (RAM), read only memories (ROM) and peripheral interface adaptors coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU). Each peripheral interface adaptor includes a control register loadable under program control. The contents of the control register control selection of several registers within the interface adaptor. The control register also controls other functions of the peripheral interface adaptor, including determining direction of data movement at the peripheral buffers of the interface adaptor. The contents of the control register of each interface adaptor are monitorable by the microprocessor unit.
    Type: Grant
    Filed: January 30, 1979
    Date of Patent: April 21, 1981
    Assignee: Motorola, Inc.
    Inventors: Thomas H. Bennett, Earl F. Carlow, Edward C. Hepworth, Wilbur L. Mathys, William D. Mensch, Jr., Rodney H. Orgill, Charles I. Peddle, Michael F. Wiles
  • Patent number: 4262338
    Abstract: A display system employs electronic components for deriving and supplying display control signals, preferably in the form of multi-bit display control words, to control a display device formed of a plurality of individual display units preferably arranged in horizontal rows and vertical columns. Each of the display units is controlled by at least one bit of a multi-bit display control word. Each vertical column of the display device is collectively controlled in whole or in part by one multi-bit display control word. Control and memory elements control the display device in accordance with a plurality of display control words received. The control and memory elements include a first level memory such as a shift register, and a second level memory such as a latch. Display control words are shifted sequentially into the first level memory until the plurality of display control words is positioned at desired memory locations.
    Type: Grant
    Filed: May 19, 1978
    Date of Patent: April 14, 1981
    Inventor: John J. Gaudio, Jr.
  • Patent number: 4261033
    Abstract: A communications processor is coupled between a main memory and a plurality of communications channels and with a central processing unit and includes control mechanisms for processing the transfer of information between the processor and the main memory with minimum interruption of the central processing unit. The processor further includes control tables and a plurality of control routines enabling the processing of the transfer of the information between the processor and the channels. The routines are unique to the communications channel characteristics of the device coupled with the channel being serviced and is configurable to reflect any changes made in such characteristics.
    Type: Grant
    Filed: January 19, 1977
    Date of Patent: April 7, 1981
    Assignee: Honeywell Information Systems Inc.
    Inventors: Richard A. Lemay, Robert E. Huettner, John P. Grandmaison, John H. Vernon
  • Patent number: 4258419
    Abstract: A Central Processing Unit provides programmable variation of the operand width for processor operations. The operands are formed with one or more N-bit segments. The CPU includes an arithmetic logic unit (ALU) which is adapted to operate serially on one N-bit segment of the operand at a time beginning with the least significant segment and repeating the operation on the remaining segments according to their order of significance. The number of repetitions of an ALU operation is controlled by a code stored in an op-code extension register (OER). The code in the OER can be changed by means of an instruction for transferring a new code to OER.
    Type: Grant
    Filed: December 29, 1978
    Date of Patent: March 24, 1981
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Donald E. Blahut, David H. Copp, Daniel C. Stanzione
  • Patent number: 4255796
    Abstract: An associative information retrieval system accepts information from a user and generates a query mask utilizing nested superimposed code words to search through and to find partial matches with the content of an auxiliary store. The auxiliary store contains similarly generated code words each produced from attribute values of records on a central store. The user information is put through the system on a character-by-character basis and the user is fed back information on the number of possible matches. The feedback informs the user on the incremental progress of the search produced in response to each newly entered character and also as part of a sequence that it may form with previously entered characters. The feedback information helps the user direct the search which the person does by supplying additional characters.
    Type: Grant
    Filed: February 14, 1978
    Date of Patent: March 10, 1981
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: John D. Gabbe, Charles N. Judice, Thomas B. London