Abstract: Virtual addressing apparatus for implementing a large virtual address in a computer system having narrow data paths, ALU, and local storage register arrays without requiring multiple passes. The virtual addressing apparatus stores the segment portion of a virtual address in a segment register and the offset portion of the virtual address in an offset register. To form a new virtual address, a new offset value is obtained by adding the displacement value given by the instruction in the instruction buffer register to the offset value stored in the offset register. The segment portion of the virtual address does not participate in the arithmetic operation for forming the new virtual address. The segment and offset portions are concatenated to form the new virtual address which is then translated to a main store address. Overflow detection circuitry in the ALU detects if an overflow out of the offset occurs as a result of the ALU operation for obtaining the new offset value.

Abstract: An interface device to provide a data and address path between a data processor, a memory and peripheral devices. The interface device includes an internal arithmetic and logic unit to provide a means for generating and/or modifying addresses for the memory or peripheral devices. The device further includes a plurality of registers for temporarily storing data or addresses as well as information associated with addressing functions, for example, program counter, index register, stack pointer and page addresses. The interface device may be used singly or in combination with like devices as in a slice processing system.

Abstract: A text-editing system having a keyboard for the input of character and text-editing operation signals, writable text storage, display and writable display storage, and control storage storing groups of microinstructions. A system control is responsive to an interrupt signal from the keyboard for decoding an input signal and deriving therefrom internal control signals for operation of the system, including modification of the display storage and text storage. Apparatus is provided for inputting the character and text-editing operation signals in either of two alternative modes. A select/store circuit is responsive to a select/store signal to select from the text storage character and operation signals modified according to a first alternative mode and to store them in a special condition storage. The system control is thereafter responsive to a recall signal to disable the keyboard interrupt, retrieve the stored signals, and operate according to them.

Abstract: An adapter converts an instruction-controlled processor such as a microprocessor into a PROM programming apparatus. The adapter is compatible with the type of processor having readout circuitry for applying a multibit signal via an internal address bus to a processor socket into which an addressable memory such as an already programmed PROM is inserted for normal processor operation. During a programming operation, the processor socket does not contain a PROM; instead, the adapter is connected between the processor socket and a PROM being programmed. Control circuitry in the adapter receives the multibit signal so as to control the entering of a plurality of data words into the PROM.

Abstract: In a special safety switch mechanism several processing units are arranged in pairs and form an original processing channel and a synchronously operated complementary processing channel which are operated dynamically and alternately in positive and negative logic, in successive processing steps, while using rectangular signal voltages of a given frequency at 180.degree. phase shift for the two logical values ZERO and ONE of the switching variables. During an operation, the signal anti-valency applied to the processing channels is continuously examined. In each processing channel, two-read-only memories are provided for storing fixed values in the form of original and complementary information which are alternately and in successive processing steps connected with the safety switch mechanism for information output.

Abstract: A microprocessor monitor or analyzer used as a test and troubleshooting tool for both the software and hardware of microprocessor based equipment. The analyzer is usable with all microprocessor families having accessible or reconstructible address and data busses up to 16 bits wide each. It has search modes that find and identify the first and last instruction in a program loop. A transfer mode permits stepping forward or backward through programs without setting addresses. It can be used as a passive real time address and data bus monitor or as an interactive break point generator. After a match address is encountered, strobing and storing of the address and data bus content can be delayed by a preset number of machine cycles, instruction cycles, loop cycles (loop being the repetitive execution of the same instruction) or combinations of these delays. After a halt or break, the processor can be stepped in single or multiple step increments according to the above cycles.

Abstract: Apparatus for use within a virtual memory data processing system offering a way of protecting data used at one interrupt level state from unauthorized use at another interrupt level state. A virtual memory data processing system permits a computer program to specify relative (or virtual) addresses rather than physical (or real) addresses. Most practical virtual memory data processing systems utilize a Virtual Address Translator (VAT), often called a Directory Look-Aside Table (DLAT). The VAT contains a plurality of internal conversion tables which perform virtual address to real address translation. A binary code, called the Interrupt Level Code (ILC), is appended to the virtual address of entries within the plurality of internal conversion tables within the VAT to permit the VAT to translate virtual addresses to real addresses only if the present Central Processing Unit (CPU) interrupt level state corresponds to the interrupt level state denoted by the ILC within the VAT.

Abstract: A data masking device having a first memory for storing information code signals convertible into visible information and a second memory containing specific code signals in locations corresponding to the code signals in the first memory which selectively are not to be visualized. Signals from each memory are simultaneously read out and a detector detects the read-out of a specific code. When the device is in a mask mode and a specific code signal is detected, the information code signal corresponding to the detected specific code is masked, i.e. it is either not visualized or else a special mark is visualized in its place. When the device is in an unmask mode, the information code signals are converted into visualized information irrespective of the detection of a specific code signal during read-out.

Abstract: Apparatus wherein a sequence of control instructions and a number of insertion instructions are stored in memory element groups of a memory accessed by associated addresses in a stored program controlled telecommunication system. The sequence is read and decoded in response to successive address increments. In order to insert one of the insertion instructions between the control instructions, the sequence includes an insertion step or reference indicating a first address assigned to the insertion instruction and a second address assigned to one of the control instructions. Upon decoding the insertion reference, a logical buffering unit is used in order to replace the successive address incrementing by such address transfers that the control instruction accessed by the second address is decoded subsequent to the insertion instruction which itself is decoded after the insertion reference.

Abstract: Decision and control logic for use in digital computers that operate in cycles provides binary valued decision signals for effecting decisional control within the computer such as that utilized in conditional branching. The decision signals are provided in accordance with binary valued control functions of binary valued static and dynamic control variables utilized in the computer. The dynamic control variables are available in a computer cycle subsequent to the availability of the static variables and represent conditions of various components of the computer. Truth tables of the control functions are stored in logic function memories addressed by logic function selection control fields of computer control words, the control fields selectively addressing the truth tables in accordance with the desired functions.

Abstract: Apparatus for determining the next data word of a requested block of data words in interlaced rotating mass memories to enable transfer of the requested block from other than the first word in the block to reduce the effective average latency. The system assumes the use of a memory storage element which is read in a serial rotational fashion (e.g., drum, disk, charge coupled device, etc.). The present invention compares the address of the data requested by a Central Processor Unit (CPU) with the address from the interlaced memory storage element that indicates its present rotational position. From these addresses, it computes the address of the next accessible cell within the requested block and transfers that address to the CPU to enable it to access the requested block at the earliest possible time.

Abstract: A data transfer or replacement system for shifting blocks of data or pages between a high speed, low capacity, working memory and a low speed, high capacity backup store of a data processing system. Each block in the working memory is associated with an "A" and a "B" single bit register. Usage bits are initially inserted into the "A" registers as information from the block is utilized. After one-half of the "A" registers have been identified by associated usage bits, the "B" single bit registers are cleared, and usage bits are inserted into these "B" registers. When one-half of the "B" usage registers are "marked", the "A" registers are cleared and usage bits are then inserted in these "A" registers. Upon the necessity for introduction of additional data from the backup store into the high speed, low capacity working memory, least recently used blocks are identified as those whose associated "A" and "B" registers have not been marked.

Abstract: In a microprogrammed data processing pipeline system comprising a plurality of stages, microinstructions for controlling the stages are stored as templates in an addressable template micromemory store and are provided automatically and sequentially to the stage of the pipeline system. Each template is associated with an individual set of data and includes microinstructions for each stage, whether real or virtual, through which the associated set of data passes. The template micromemory store is segmented into a plurality of individually addressable micromemory units with each unit therein storing microinstructions for an individually associated stage in the data processing pipeline system.

Abstract: A system for transmitting binary instruction or data words to or from a computer by control from a home base remote from the computer site, and characterized by the entry of signals into the computer or the extraction of signals from the computer performed by apparatus which directly connects to the computer console manual switches and indicator lights. A single telephone line forming two simultaneously active channels transmitting time-spaced pulses in opposite directions, by modems known in the art, is used as the communication link. A special purpose microcomputer directly connected to the main computer console acts figuratively to actuate the console push buttom switches in response to pulse train signals received from home base and representing single bits or multibit words. It returns to the home base a rapidly iterated and updated pulse train representative of the status of all console lights.

Abstract: A data processing system in which a central processor polls one or more peripheral devices to initiate a data transfer or to enable a data transfer. The system includes logic associated with a peripheral device or with an interface device for sensing the occurrence of data handling errors such as parity errors, carrier loss, clear to send loss, data overrun or underflow, and for interrupting the central processor upon such occurrence to avoid polling that peripheral device unnecessarily. A status signal is also generated to inform the processor of the nature of the interrupt, so as to distinguish from, for example, the interrupt of another device which is operative to communicate by means of such interrupt rather than by polling.

Abstract: In a microprogrammed data processing pipeline system comprising a plurality of stages, microinstructions for controlling the stages are stored as templates in an addressable template micromemory store and are provided automatically and sequentially to the stages of the pipeline system. Operation microcode is introduced for a particular stage after the templates are issued from the micromemory store but before provision thereof to the pipeline system, thereby allowing a single template to control a plurality of different operations of a particular stage within the pipeline system. Provision is also made to freeze or inhibit the issuance of subsequent templates during the execution of excessively long operations in the particular stage.

Abstract: A multiprogramming/multiprocessing computer system for executing a plurality of processes sharing common information in the form of records, pages or messages, employing an apparatus for avoiding an interference between two processes seeking access to elements of common information. The system operates to store in a first memory utilization data in table form identifying the processes which have accessed each individual element of common information. A second memory stores a matrix of precedence data representing the relative order in which processes must access the common information in accordance with a predetermined set of access rules. When a first process enters a request to access an element of common information, the system identifies from the utilization table any other process which, according to the access rules, must be given precedence to the common information over the first process.

Abstract: A Computer system which includes a central processing unit, a central memory storage unit and a plurality of peripheral devices, the central processing unit having a control unit for dividing single complete input/output instructions for the transfer of data within the system into a sequence of discrete, separately executable, time independent operation instructions under the control of a microprogram. The system further includes peripheral device control units for the control of the independent execution of the discrete divided input/output (I/O) operation instructions. A microprogram command line is connected to the control unit in the central processing unit for controlling the output of the discrete I/O operation instructions along the system bus.

Abstract: An alignment network between N parallel data input ports and N parallel data outputs includes a first and a second barrel switch. The first barrel switch fed by the N parallel input ports shifts the N outputs thereof and in turn feeds the N-1 input data paths of the second barrel switch according to the relationship X=k.sup.y modulo N wherein x represents the output data path ordering of the first barrel switch, y represents the input data path ordering of the second barrel switch, and k equals a primitive root of the number N. The zero (0) ordered output data path of the first barrel switch is fed directly to the zero ordered output port. The N-1 output data paths of the second barrel switch are connected to the N output ports in the reverse ordering of the connections between the output data paths of the first barrel switch and the input data paths of the second barrel switch.

Abstract: A data processing device for variable length formats includes a control unit and a storage unit coupled to the control unit. Two data exchange buses are each coupled to a respective data input and to a respective data output of the storage unit. Two switches are coupled to the control unit and to respective data exchange buses. An arithmetic/logic unit is coupled to the control unit, to the switches and to the storage unit. A data shaft unit is coupled to the data exchange buses and to the control unit. A data masking unit is coupled to the data exchange buses, to the control unit and to the switches. This device enables the preparation for processing of multibyte data fields arbitrarily arranged with respect to the word boundaries in main storage. The data shift unit provides automatic alignment of the bytes of the operands relative to each other. The data masking unit masks irrelevant bytes of the first and last words of each operand.