Abstract: The present invention is directed to a relational data base system which is operating in a virtual machine environment. The invention provides a system that includes a disconnected virtual machine which is running in the same virtual machine environment as is the relational data base. Insert and Update requests to the system are generated by programs running in user controlled virtual machines. Other users issue select and view requests which lock out insert and update requests which relate to the same data domain. With the present invention Insert and Update requests go to the disconnected virtual machine which ques them and applies them against the relational data base in the order that the requests are received. In this way, while a select is being executed on data in a particular domain of the data base, update and insert request for the same domain will be held by the virtual machine and the operator will not be "locked out" of the system.

Abstract: In a typewriter having a microprocessor for processing stored data according to a stored program, a method for detecting that a machine cover has been opened for servicing and for interrupting a data processing cycle in progress for as long as the cover remains open, said method including, in response to said interruption, the steps of storing in a portion of memory all data, addresses and flags required for the later continuation of the control cycle so that the programmable control unit can subsequently be brought into a condition in which it is insensitive to a great extent to the consequences of electrostatic discharges as may occur during servicing, and after closure of said machine cover after servicing, reconstructing the status of the control cycle prior to the termination, by entering the data, addresses and flags stored in memory into appropriate working registers and buffers.

Abstract: A system for communicating between a plurality of nodes in a computer, each node including logic circuitry or transmitting and receiving data at first and second logic levels. The system includes an arbiter coupled to the nodes for detecting a lack of request activity from the nodes. A default generator is connected to the arbiter and responds to a lack of request activity and the absence of a multi-cycle data transfer being performed on the bus and causes the bus to be driven to one of the first and second logic levels.

Abstract: An address boundary detector is disclosed that functions with an arithmetic logic unit (ALU) in a computer processor while the ALU generates addresses by adding an offset or displacement to a base address. The detector monitors bits of addresses to determine whether a data item can be completely stored within the same block or page of memory as that addressed by the base address from which it was derived.

Abstract: ERASE INPUT support is provided for the optimizer system disclosed in commonly-assigned co-pending application Ser. No. 827,767, now U.S. Pat. No. 4,750,137, by altering the programming of the optimizer system so that the only MDT flags turned off in the optimized outgoing data stream are those associated with protected pre-modified fields. The programming is further altered so that when an incoming data stream is received by the optimizer system, all unprotected fields in the present-state image are preprocessed prior to being updated from the incoming data stream to reflect the information available to the optimizer system as to whether the ERASE INPUT key has been pressed.

Abstract: A signal generator provides circular addressing, i.e., performs basic modulo boundary indexing, which includes both positive and negative addressing, by adding an increment to a base register until a modulo boundary is reached without permitting the carry bit to propagate but instead resetting the address back to its lowest value. More particularly, the invention provides a signal generator which includes an adder having base address signals applied thereto from one of a plurality of registers and having an operand such as signals from an instruction data register (IDR) also applied thereto. Selected most significant bits from the output of the adder are applied to the input of a modulo mask function unit. Also applied to the input of the modulo mask function is a number of most significant bits of the base address signal. The carry bit from the adder is also applied to the input of the modulo mask function unit.

Abstract: An in-storage table pair structure is disclosed which extends to the user of the data processing system the internal structures of a component of the operating system. The table pair structure includes pairs of tables that are pointed to by a table pair pointer. A table pair pointer is a double word of virtual storage in which the first word is the address of a user-defined table and the second word is the address of a developer-supplied table. Both tables form a table pair. The table pairs permit functional routines (IETDFs) to reference data in both developer-supplied tables as well as user-defined tables in order to tailor a component of the operating system. The IETDF locates a particular table, or set of tables, by first referencing a global control block which contains addresses of two router control blocks.

Abstract: Electronic payment method wherein a memory is used with two zones of equal capacity, a payment zone and a reloading zone. A stop-bit equal to "0" is written in the payment zone. A first payment of a certain amount is obtained by counting an amount equal to the payment of "1's" in the payment zone starting from the first bit in the memory. A "0" is written accordingly. A second payment of any other amount is obtained by counting another amount of "1's" equal to the new payment starting from the preceeding "0" and a "0" is written and so on until the rank of the bit to be written as "0" in the payment zone overshoots the rank of the stop-bit in the reloading zone. For a reloading operation a "0" is written in the reloading zone for all bits having the same rank as the "0" bits in the payment zone and a new stop-bit is determined and this is set equal to "0" by writing in the reloading zone.

Abstract: A data processing arrangement intended for use, inter alia, in a multi-processing system for use in association with a systolic array is implemented on a single semiconductor chip. The arrangement includes processing means (AU, MU) and storage means (ACC), interconnectable via an electronic equivalent (MM) of a cross-bar switch.

Abstract: A method for controlling processor access to input/output control units and devices connected to the control units to prevent control unit and device lookout due to the condition where the channel turn-around time becomes less than the device controller's housekeeping time is disclosed. The problem of control unit and device lockout is overcome by monitoring path and device activity for a given processor while at the same time keeping track of other processors waiting for a given path and device. When it is determined that a given number of consecutive input/output operations have been accomplished for a given processor and at the same time another processor requires this resource, then a busy condition will be asserted for new input/output requests from the current processor for the currently accessed path and/or device. This action forces the offending processor to wait until the controller and/or the device is again available.