Abstract: A virtual storage address space access control system has an access register having a plurality of access register numbers, a dynamic address translation unit and translation lookaside buffer for translating a virtual address to a real address by using a segment table designation. It further comprises first and second control registers for designating primary and secondary spaces, respectively, the primary and secondary spaces being accessed when the content of the access register is "1" or "0". Also included are access register translation lookaside buffer for indirectly obtaining a segment table designation by using a content of the access register and access register auxiliary translation lookaside buffer for directly obtaining the segment table designation by using the access register number.

Abstract: In a parallel processing architecture following the Single Instruction stream Multiple Data stream execution paradigm where a controller element is connected to at least one processing element with a local memory having a local memory address shift register adapted to receive and retain therein a globally broadcast memory base register address value received from the controller element for use by the processing element for access and transfer of data between the processing element and its respective local memory, a computer architecture for implementing indirect addressing and look-up tables includes a processing element shift register associated with the at least one processing element and adapted to receive and retain therein a local memory offset address value calculated or loaded by the associated processing element in accord with a first predetermined set of instructions.

Abstract: A write-back coherency system is used, in an exemplary embodiment, to implement write-back caching in an x86 processor installed in a multi-master computer system that does not support a write-back protocol for maintaining coherency between an internal cache and main memory during DMA operations. The write-back coherency system interrupts the normal bus arbitration operation to allow export of dirty data, and includes an X%DIRTY latency-control function. In response to an arbitration-request (such as HOLD), if the internal cache contains dirty data, the processor is inhibited from providing arbitration-acknowledge (such as HLDA) until the dirty data is exported (the cache is dynamically switched to write-through mode to prevent data in the cache from being made dirty while the bus is arbitrated away).

Abstract: A cache tag memory device having a memory array comprising a first single-port memory array, a second single-port memory array, and a dual-port memory array. A first port, accessed by a local processor, may read from and write to its corresponding single-port memory array and the dual-port memory array. A second port, accessed through a global system bus, may also read from and write to its corresponding second single-port memory array and the dual-port memory array. Both ports operate asynchronously relative to each other. Status bits indicating the status of the entries in the first and second single-port memory arrays are stored in the dual-port memory array and may be altered by the global system while the local processor is performing its operations.

Abstract: An adder adds a displacement address to a base address to generate a virtual address. The adder includes carry indicating circuitry for generating a carry indicating signal indicating whether the addition of the displacement address to the base address resulted in a carry. Addressing circuitry addresses the translation memory with a subset of bits from the base address so that the translation memory outputs multiple address translation entries simultaneously. At approximately the same time the translation memory outputs the multiple address translation entries, the adder completes the addition of the displacement address to the base address and generates the carry indicating signal. A multiplexer selects one of the address translations output from the translation memory in response to the carry indicating signal.

Abstract: A Register Alias Table (RAT), including a retirement floating point RAT array, for floating point register renaming within a superscalar microprocessor capable of speculative execution. The RAT provides register renaming floating point registers to take advantage of a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set (such as the Intel architecture or PowerPC or Alpha designs) and thereby eliminate false data dependencies that reduce overall superscalar processing performance. As a set of uops is presented to the floating point RAT logic, their logical sources are used as indices into a floating point RAT array to look up the corresponding physical registers which reside within a Re-Order Buffer (ROB) where the data for these logical sources is found.

Abstract: A dynamic address translation processing apparatus in a data processing system having a main memory for storing an address conversion table, and a central processing unit for converting a virtual address to a real address by referring the address conversion table. The central processing unit includes a first register for holding the virtual address, a second register for holding a table entry of the address conversion table corresponding to the virtual address held in the first register and, having an update bit indicative that a page in memory has been written to a third register for holding the real address of the table entry held in the second register, a comparison circuit for comparing the virtual address held in the first register with the other virtual address to be converted to the real address, and an update unit for updating the update bit in the table entry held in the second register.

Abstract: A dynamic random access memory with two divided memory banks is disclosed wherein memory cells are divided into first and second groups each of which includes an array of memory cells connected to a corresponding word line. Those memory cells are subdivided into subgroups each of which has four memory cells. A first set of input/output lines is provided for the first group of memory cells, and a second set of input/output lines is provided for the second group of memory cells. An output circuit section is connected to the those sets of input/output lines to output data transferred thereto. An access controller section specifies subgroups alternately from the first and second groups of memory cells with four memory cells as a substantial access minimum unit, accesses memory cells of a specified subgroup to read stored data therefrom and transfers the read data to corresponding input/output lines associated therewith.

Abstract: In an apparatus for use in a computer system for accessing to a main memory when a desired datum is not memorized in a cache memory, a supplementary memory is included in the apparatus for memorizing a supplementary datum representative of a predetermined address in the main memory. When the desired datum is not memorized in a particular address of the cache memory, a judging circuit produces a particular signal. By a combination of the supplementary datum and the particular signal, an access control part accesses to the main memory to read a specific datum of the main data as the desired datum from the main memory. The specific datum is stored in the particular address from the access control part. The described system can be used for both tagged and untagged data, allowing for compatibility between data systems using different tagging schemes.

Abstract: A logic circuit for a content-addressable-memory or parallel-processor array cell implements both prioritizing and counting functions for response resolution. It includes a means for receiving from a prior cell a response-resolution token and a means for receiving the positive or negative response of the current cell to a pattern to be matched. It also includes a means for deriving as a function of the prior cell's response-resolution token a response-resolution token for the current cell that implements prioritization and counting response-resolution functions for positive or negative pattern-matching responses of the current cell. Finally, it includes a means for selecting for the current cell the appropriate response-resolution token based on the cell's positive or negative pattern-matching response and a means for sending that response-resolution token to a subsequent cell.

Abstract: A method for detecting a half-full condition of a first-in, first-out memory array. The method of the invention includes the steps of a) moving a write pointer through the array to write data to alternating rows of the memory array; b) moving a read pointer through the array to read data from the alternating rows of the memory array in first-in, first-out order; and c) providing a half-full indication when the read pointer and the write pointer point to adjacent rows in the memory array. This method eliminates the need to route lines across the array to detect a half-full condition, thereby reducing die and power requirements and offering an increase in speed.

Abstract: Under such a condition between outputs of AND circuits for outputting All "0" when one of zero detecting circuits of two register identifiers within an instruction register detects "0", instead of a content of a general-purpose register designated by these identifiers, and also a carry derived from a page offset corresponding to an intermediate result of an address adder, when a page address portion of a logical address is known before this logical address is defined, selecting circuits are controlled, and then the address controller is bypassed to retrieve a translation look-aside buffer, thereby defining a real address. In case that the page address portion of the logical address register is identical to the page address portion of the base register, the translation look-aside buffer is previously retrieved in accordance with either the content of the index register, or the content of the base register so that the real address can be defined.

Abstract: To provide for fast access times with very large key fields, an associative memory utilizes a location addressable memory and look up tables to generate from a key an address in memory storing an associated record. The look up tables, stored in a memory, are constructed with the aid of arithmetic data compression methods to create a near perfect hashing of the keys. For encoding into the look up table, keys are divided into a string of symbols. Each symbol is assigned an index value, such that a sum of index values for symbols of a particular key is a unique value that is used as an address to the memory storing the record associated with that key.

Abstract: Memory system for internally rearranging fields in database records. The memory is separated into modules, each module separately addressable. Each memory module is addressed by selectively modifying a supplied address, for example by the output from exclusive-OR gates, having inputs from the address supplied to the memory system and another inputs from address modification registers. The address modification registers are selectively set by the external utilization device to permit reading different rows in the memory modules, The data output columns from the memory modules can be rearranged using selector devices such as demultiplexors. Data can be masked by precluding certain selector control signals.

Abstract: A computer system where memory access is accelerated by automatically incrementing the address at the memory chip inputs, as soon as the minimum hold time has occurred. If the next address actually requested by the CPU does not match this predicted address, then the actual address is driven onto the chip inputs as usual, so essentially no time is lost. However, if the automatically incremented address does match the next actually requested address, then a significant fraction of the chip's required access time has been saved.

Abstract: A Tag Field for a second level cache memory subsystem in a PC is provided which replaces the fixed Valid and Dirty bits with programmable bits which can each be programmed as a Valid bit, a Dirty bit, or an additional address bit. The cacheable address space of the PC can thus be increased by programming one or more of the two programmable bits as additional address bits. This method can be implemented on existing computers by modifying the system or application software to utilize these programmable bits in a manner to achieve more optimum performance of the cache.

Abstract: A control circuit for data transfer between a main memory and a register file. Firstly, the control circuit acquires, via a selector, a save area mask (SAM) data from external circuitry. A register file address generator produces a register file address using the SAM data which has been chosen by the selector. The register file address determines a location of a register in the register file. A SAM data renewal circuit is provided to renew the SAM data selected by the selector. The SAM data which has been renewed will be used for addressing another register in the register file. The renewal circuit supplies the selector with the SAM data which has been renewed. A controller is arranged to receive the SAM data chosen by the selector and generates a control signal according thereto. The control signal is applied to the selector and controls same such as to select the SAM data from the external circuit or the SAM data applied from the SAM data renewal circuit.

Abstract: A method for reducing the number of bits in a binary word (AI) which represent a series of addresses, called initial addresses, having a first step (E1) which successively extracts from each initial address (AI) at least one bit (C1) with a fixed rank; forms (1) an address called the selection address (AS) from each bit or bits (C1); extracts from each initial address (AI) a series of bits (C3, C6) using a format (M1i) selected from multiple predetermined first formats (M11, M12, M13, M14), as a function of the selection address; forms (2) with this series of bits (C3, C6) a binary word called the first relative address (AV1); and adds this first relative address to an address called the predetermined basic address (AB(M1i)) associated with the format (M1i) selected to determine this first relative address so as to obtain an address called the first reduced address (AT1) having a smaller number of bits than the initial address (AI); and wherein the basic address (AB(M1 i)) associated with the one (M1i) in the

Abstract: Sense amplifiers provided for each of the bit line pairs are divided into groups to be independently driven, whereby the influence of sense amplifiers of different groups can be prevented, and therefore the destruction of data of the non-selected memory cells during data transfer can be prevented. In transferring data from the data register to the memory cell array, the sense amplifier is not activated until the stored information of the memory cells selected by the word line is fully read to the corresponding bit lines, whereby the destruction of data stored in the non-selected memory cells can be prevented.

Abstract: A memory device comprises a dynamic random access memory (DRAM) organized by page and a memory access devices. The DRAM corresponding to the pages is divided into a plurality of groups each constituted of pages for storing data which are unlikely to give rise to interference between pages. The DRAM of each group is constituted as a memory system which responds to page access. The memory access devices are provided separately for the memory system of each group. Each memory access device has a memory means which, in response to an access designating a page address of the memory system associated therewith, stores an old page address designated at least one access earlier, and judging means which, in response to said page address access, judges whether or not the new page address designated by said access coincides with said old page address stored in said storage means.