Abstract: Enables a host (hypervisor) to access any location in any guest zone in a large memory, when host and guest operands have small addresses that cannot access locations outside of their own zones. System hardware/microcode provides a particular number of windows for host use. Each CPU in the system has one or more window access registers (WARs), and one or more window registers (WRs). The host uses a load WAR instruction to designate each page frame (PF) in the host zone to be used as a host window, and each PF is associated with a respective window number. When the host receives an interception signal requiring the host to access a guest location represented by a guest zone identifier and a guest small address, the host designates one of its window numbers for an access to this guest location.

Abstract: A method and an apparatus for configuring multiple absolute address spaces are disclosed which simultaneously operate a plurality of virtual machines (VMs) respectively having operating systems on a single real computer by allocating a plurality of logical address spaces to an absolute address space. A different absolute address space is allocated to each of the VMs, whereby the respective VMs can access a main storage with a designated address without adding a constant to the designated address.

Abstract: A data register file system is provided in a microprocessor having a pipelined execution unit that employs the data register file to store operands and results of its instruction executions. The data register file system includes a plurality of data registers, each of which stores one of the operands and results. A pointer table has a plurality of pointer registers, each storing an address of one of the data registers. A first address generation logic is coupled to the pointer table and the pipelined execution unit for generating a first set of pointer table addresses to access a first group of the pointer registers for the addresses of a first group of the data registers which are required by the execution of a first floating point instruction.

Abstract: A bit addressing system is disclosed in which on N-bit long addressing for the main storage is executed by means of a computation including a plurality of fields in an addressing operand. When there exist predetermined fields in the addressing operand, the value determined by the fields is regarded as the value for the bit unit in the two's complement representation, and a base address and a bit offset are generated by adding the value obtained by shifting the bit unit value by M bits in the direction of the lower order bits, to the address of the byte unit. Namely, it becomes possible to designate two effective addresses of a base address which is a byte address and a bit offset which is the bit displacement from the base address by means of a single operand. The range of designation of the bit offset is from -2.sup.N-1 bit to (+2.sup.N-1 -1) bit, and it is possible to designate the range of 2.sup.N+M bits as bit addresses.

Abstract: An expandable memory system including a central memory controller and one or more plug-in memory modules, each memory module having an on-board memory module controller coupled in a serial network architecture which forms a memory command link Each memory module controller is serially linked to the central memory controller. The memory system is automatically configured by the central controller, each memory module in the system is assigned a base address, in turn, to define a contiguous memory space without user intervention or the requirement to physically reset switches. The memory system includes the capability to disable and bypass bad memory modules and reassign memory addresses without leaving useable memory unallocated.

Abstract: An apparatus and method for supplying an address and data to an external memory device. The number of pins available for supplying the address is less than the number of address lines required at the external memory device. A register is used to store the high order bits of the address and is pre-loaded with a default page value. An output of the register is coupled to an address input of the external memory. If the high order bits of the address are equal to the default page value, a control device couples the data lines directly to the external memory device and a read or write operation follows. If the two values are different, a paging cycle is performed where the high order address bits are latched through the register to the address input of the external memory and then the data bits are coupled to the external memory device.

Abstract: A processor data memory address generator is adapted to receive a control word from a program controller receiving instructions from a program memory addressed by an instruction counter and producing a program signal addressed to an arithmetic and logic unit. The instruction counter is incremented by a clock signal and reset by the program controller. The control word comprises location information and selection information and the address generator is adapted to produce a data address having a first part comprising bits of said location information and a second part formed by a selected set of bits of the address of the current instruction identified by said selection information.

Abstract: A circuit configuration for adapting a logical address space of a processor unit to a physical address space of a memory includes, an interpretation unit, and data and control lines connecting the interpretation unit to the processor unit. The interpretation unit includes a register having a first register region and having a second register region to be written into by the processor unit. The interpretation unit continuously evaluates a logic state of the processor unit, writes contents of the second register region into the first register region at defined logic states and outputs contents of the first register region as an address. A linking unit is connected by address lines to the processor unit, to the interpretation unit and to the memory. The linking unit forms a total address for the memory from addresses transferred by the interpretation unit and the processor unit.

Abstract: An N-word write access memory is described. Using a variation of conventional control signals RAS, CAS, WE and OE, an innovative scheme of signal protocol allows the N-bit word write memory to have an input/output bandwidth double that attained in the prior art, using substantially the same components and without affecting the bit-width, hence, the pin-count, of the external data bus.

Abstract: An information processing network includes multiple processing devices, a main storage memory, one or more disk drives or other auxiliary storage devices, and an interface for coupling the processing devices to the main storage memory and the auxiliary devices. A primary directory in main storage contains mapping information for translating virtual addresses to real addresses in main storage. Look-aside buffers in the processing devices duplicate some of the mapping information. A primary directory hardware lock, subject to exclusive control by any one of the processing devices to update the primary directory, inhibits access to the primary directory based on hardware address translations initiated when one of the processors holds the primary directory lock. Address translations in progress when the lock is acquired proceed to completion before the primary directory is updated under the lock. Accordingly, such updates proceed atomically relative to hardware primary directory searches.

Abstract: A memory device comprises a dynamic random access memory (DRAM) organized by page and a memory access devices. The DRAM corresponding to the pages is divided into a plurality of groups each constituted of pages for storing data which are unlikely to give rise to interference between pages. The DRAM of each group is constituted as a memory system which responds to page access. The memory access devices are provided separately for the memory system of each group. Each memory access device has a memory means which, in response to an access designating a page address of the memory system associated therewith, stores an old page address designated at least one access earlier, and judging means which, in response to said page address access, judges whether or not the new page address designated by said access coincides with said old page address stored in said storage means.

Abstract: A method and apparatus for selecting an entry to be replaced in a translation lookaside buffer in a computer system. The translation lookaside buffer stores a plurality of entries of virtual-to-physical address translations with each entry having a used bit and a valid bit.

Abstract: A random access array memory device which uses a static buffer as a cache for speeding the access times achievable for data retrieval from the device. The static buffer is operationally divided into two or more blocks so that each block holds a block of data from a different row of the array. The division of a single buffer into several operational blocks significantly increases the "hit" probability of the cache, allowing fast access from the buffer. A control system stores the row address (TAG) of each of the multiple blocks and compares that address to the row address of the data desired and signals the result of that comparison. Random access memory arrays of the multiple line cache configuration are employed in data processing systems including a CPU, address and data buses, control logic, and multiplexers.

Abstract: An apparatus and method for performing rotation of data in a register file memory. The apparatus utilizes a rotation address generator including rotation value, modulus, and offset registers, a comparator, a data selector, logic circuitry, and a subtractor. A predetermined area (P.times.Q) of the register file memory and a rotation value corresponding to the number of bits to be rotated in the rotation area is designated by an instruction program memory. An instruction decoder signals the register file, modulus register, rotation value register, and offset register of an impending rotation of data, thereby enabling loading of the modulus and rotation value registers and resetting of the offset register. A counter provides a relative address to the comparator and data selector.

Abstract: A circuit is provided for replacing a defective signal path (94) of a plurality of like signal paths with a redundant signal path (95, 96). A redundant decoder (72) is programmable to respond to a plurality of predetermined addressing signals (RFn) that normally operate to address the defective signal path (94, ROWL1R and ROWLIL). The redundant decoder is operable to generate a disable signal (RREN) in response to the predetermined addressing signals (RFn) and also is operable to select a redundant signal path (95, 96) in response thereto. A decoding circuit (70, 74) normally decodes selected ones of a plurality of addressing signals (RFn) and selects at least one of a plurality of signal paths in response thereto. The decoding circuit (70, 74) is coupled to the redundant decoder (72) for receiving the disable signal (RREN) therefrom. In response to receiving this disable signal (RREN) the decoding circuit (70, 74) will not decode the preselected addressing signals (RFn).

Abstract: An apparatus for temporarily disabling a translation lookaside buffer in a computer system upon the occurrence of certain predefined system conditions. Such conditions may be of a first type which have been predetermined to indicate a greater risk that two or more virtual addresses stored in the TLB will simultaneously match the incoming virtual address, and/or of a second type in which access to the TLB is not needed. An example of the first type is a reference to an unmapped segment of memory. An example of the second type is the processing of a non-memory-access instruction. The apparatus may further include failsafe circuitry to shut down the TLB if at least a given number of matches occur at any time and for any reason, the given number being greater than 1. The apparatus prevents loss of data or damage to the chip where match comparisons are performed in parallel.

Abstract: A computer system is described having selectable pointer validation. The pointer structure is modified to provide selectable pointer validation. Each pointer comprises an effective address portion and a validation enable field. The effective address portion defines the memory location referenced by the pointer. The validation enable field comprises one or more bits of information that indicate whether or not selectable pointer validation is enabled for the particular pointer. Prior to executing a pointer reference, a processor first loads the desired condition of the validation enable field of the pointer. In normal practice of the invention, a programmer would enable selective pointer validation for particular pointers under debug testing or pointers for which a problem may have been encountered. For those pointers for which selective pointer validation is disabled, the pointer reference to the specified effective address occurs without any pointer validation processing.

Abstract: Methods and apparatus are disclosed for transferring data to and from the Local Bus of a reduced instruction set computer (RISC) system, to which a first set of high performance devices, including at least one central processor ("CPU"), is attached, and a Remote Bus, to which a second set of relatively lower performance devices is attached, in a manner that does not limit the RISC processor's performance. According to the preferred embodiment of the invention, a RISC architecture is disclosed that includes a novel data transfer controller ("DTC"), or set of DTCs, suitable for performing the aforesaid data transfer function between the high performance Local Bus and one or more Remote Buses to which complete subsystems or peripherals, typically having different (and lower) performance characteristics, are attached. The resulting RISC arthitecture permits commercially available peripherals and subsystems to be used with high performance RISC processors without limiting RISC system performance.

Abstract: A integrated mass memory device is formed by combining a piezoelectric bimorph cantilever (214) with a recording surface (212) having a number of storage locations to and from which digital information is transferred using a scanning tunneling microscope or an atomic force microscope mode of operation. Controls circuits (240) are provided for controlling the scanning of the recording surface (212) and for writing and reading information into and from the recording surface. An image storage system stores images captured from an optical sensor using piezoelectric bimorph cantilevers for reading and writing digital information on recording surfaces.

Abstract: This dynamic random access memory having a plurality of rated voltages as an operation supply voltage operates accurately with a sufficient operating margin for each rated voltage. The dynamic random access memory comprises a circuit (200; 120, 130) for generating a signal for defining operation speed/timing of a sense amplifier (50) depending on the operation supply voltage, and a circuit (210) for driving the sense amplifier in response to an output of a defining signal generating circuit. The sense amplifier driving circuit comprises a first gate (G1) for transmitting a sense amplifier activating signal as it is in response to the defining signal, a second gate (G2) for passing therethrough a sense amplifier activating signal passed through a delay circuit (100) in response to the defining signal, and transistors (25, 25'; 25) for driving the sense amplifier in response to outputs of the first and second gates. One of the first and second gates is activated by the defining signal.