Abstract: Devices, methods, and systems for shutdown and restart management in a distributed computing environment are described herein. One method includes determining whether a backup of a workload in a distributed computing environment exists, causing a shutdown sequence of the workload to occur at a first predetermined time to shut down the workload, and causing a restart sequence of the workload to occur to restart the workload in the distributed computing environment.

Abstract: A host system is coupled to a storage device and manages completion queues (CQs) for the storage device. The host system includes a host controller and memory that stores submission queues (SQs) and the CQs. The host controller fetches a command from a given SQ that corresponds to a target CQ. The host controller saves the command in an SQ internal buffer of the host controller, calculates an available capacity (AC) associated with the given SQ for the host system to store a response to the command from the storage device, and sends the command to the storage device when the available capacity is non-zero. The available capacity is calculated based on, at least in part, available slots in the target CQ.

Abstract: An information processing apparatus including a plurality of components, includes: a power circuit unit capable of switching between supplying and stopping operating power to the plurality of components; a first component of the plurality of components, the first component being related to external power supply, and being supplied with operating power directly from the power circuit unit; a second component of the plurality of components, the second component being not related to the external power supply; a switch unit connected between the power circuit unit and the second component, the switch unit being capable of switching between supplying and stopping the operating power supplied from the power circuit unit to the second component; and a sub-controller that is operable with power supply to a main controller stopped, the main controller executing information processing based on an operating system (OS).

Abstract: Garbage collection technology for non-volatile memory is shown. Space allocation of the non-volatile memory is presented by a plurality of logical-to-physical address mapping sub-tables. The processor selects a plurality of source blocks and a destination block from the non-volatile memory for garbage collection. In order from the lowest to the highest logical address, the processor selects the logical-to-physical address mapping sub-tables in turn for use as a scan target, to perform a full scan of each logical-to-physical address mapping sub-table. In this way it identifies valid data in the source blocks, collects the valid data obtained from the source blocks, and programs the valid data to the destination block.

Abstract: A method includes: generating a first sum value at least by a first resistor; generating a first shifted sum value based on the first sum value and a nonlinear function; generating a pulse number based on the first shifted sum value; and changing the first resistor based on the pulse number to adjust the first sum value.

Abstract: A memory read response is received from a memory controller in response to a memory request and includes specific data and specific metadata attendant to the specific data retrieved with specific memory addresses in the device memory. The specific data and specific metadata are sent to a host device in a host-bound memory read response. In response to determining that a metadata update condition is satisfied, a number of actions are performed as follows. Specific modified metadata attendant to the specific data is determined. A MEMC-bound memory write request for metadata update is generated. The MEMC-bound memory write request is used to write the specific modified metadata attendant to the specific data in the device memory. The specific data and the specific modified metadata are stored in an entry of a temporary write buffer until the entry is invalidated by the corresponding metadata update write acknowledgement returned from the MEMC.

Abstract: An apparatus comprises at least one processing device configured to determine, for a given portion of data to be replicated from a first multiple-tier storage system to a second multiple-tier storage system, tiering information characterizing a given storage tier of the first storage system in which the given portion of data is stored. The at least one processing device is also configured to select, based at least in part on the determined tiering information and storage tier mapping policies mapping storage tiers between the first and second multiple-tier storage systems, one of the storage tiers in the second multiple-tier storage system. The at least one processing device is further configured to replicate the given portion of data from the given storage tier of the first multiple-tier storage system to the selected storage tier of the second multiple-tier storage system.

Abstract: Examples of the present disclosure provide a memory system and operation method thereof, a memory device and operation method thereof. In one example, the operation method for the memory system includes: obtaining a wear value of a system area and a wear value of a user area within a first period of time; and determining whether to reallocate virtual blocks in a first reserved area of the system area and a second reserved area of the user area based on a result of comparison between the wear value of the system area and the wear value of the user area. Other examples are shown and described.

Abstract: A method of circuit conception of a computational memory circuit including a memory having memory cells, the method including: receiving an indication of the memory storage size and an indication of an instruction frequency of the instructions to be executed by the computational memory circuit; evaluating for a plurality of candidate types of memory cells, a number representing an average number of cycles of the memory of the computational memory circuit per instruction to be executed; determining, for each of the plurality of candidate types of memory cells, a minimum operating frequency of the computational memory circuit based on the number N and on the memory storage size; selecting one of the plurality of candidate types of memory cells based on the determined minimum operating frequency; and performing the circuit conception based on the selected type of candidate memory cell.

Abstract: The description relates to adaptive data storage management. An example manages data within a database system using dynamically adjustable mini-pages within a buffer pool. The example involves receiving a request for a data item, adjusting mini-page sizes based on the request, and determining the data item's presence within these mini-pages. Upon locating the item, the request is executed on the relevant mini-page. The example also updates a mapping table to correlate mini-page identifiers with their locations in the database, and selectively caches or evicts the data item based on probabilities and access patterns.

Abstract: A computing system is provided, including a processor configured to receive a standardized stabilizer instrument specification including an input Clifford unitary, an output Clifford unitary, and a plurality of stabilizer instrument bit matrices. The processor is further configured to receive a logical instrument input error correction code and a logical instrument output error correction code. The processor is further configured to compute a logical instrument specification based at least in part on the standardized stabilizer instrument specification, the logical instrument input error correction code, and the logical instrument output error correction code. The logical instrument specification includes a logical input Clifford unitary, a logical output Clifford unitary, a plurality of logical instrument bit matrices, and a logical instrument relabeling matrix. The processor is further configured to store the logical instrument specification in memory.

Abstract: Disclosed techniques relate to limiting a data rate of communications on fabric circuitry proportionally to a violation of a power-related threshold. Toggle rate detector circuitry, measuring a toggle rate between a given interface circuit and the fabric circuitry, may be distributed at interfaces that couple the fabric circuitry and multiple client circuits. Power control circuitry may generate an estimate of electrical current use by a given client circuit based on a toggle rate between the client circuit's interface and the fabric circuitry and based on a communication event. The power control circuitry may detect, based on the estimates of electrical current use, a violation of an electrical current threshold. Additionally, the power control circuitry may limit the data rate of communications on the fabric circuitry, proportionally to a magnitude of the violation. Disclosed techniques may mitigate violations with reduced impacts on performance relative to traditional techniques.

Abstract: A data storage technique involves detecting that candidate data is deduplicatable within a storage array. The technique further involves, in response to detecting that the candidate data is deduplicatable within the storage array, evaluating whether to perform a compression operation on the candidate data in place of performing a deduplication operation on the candidate data and providing an optimization decision indicating whether to perform the deduplication operation on the candidate data in place of performing the deduplication operation on the candidate data. The technique further involves performing, within the storage array, a storage optimization operation on the candidate data based on the optimization decision, the storage optimization operation including one of the deduplication operation to deduplicate the candidate data and the compression operation to compress the candidate data.

Abstract: A data storage device includes a relocation management system that determines whether to perform a relocation operation based on an operating temperature, performance metrics and/or energy metrics associated with the data storage device. The relocation management system uses the operating temperature to identify a performance threshold and an energy threshold. Each threshold indicates whether the relocation operation is a first relocation method or a second relocation method. If the validity count of a memory block included in the relocation operation is below each threshold, the first relocation method is selected. If the validity count of the memory block is above both thresholds, the second relocation method is selected. However, if the validity count of the memory block is in a tradeoff range, the relocation management system selects a relocation method based on a tradeoff between performance metrics and energy consumption metrics.

Abstract: An electroencephalogram (EEG) signal classification method and apparatus, a device, a storage medium, and a program product are provided, and relate to the field of signal processing technologies. The method includes: obtaining a first EEG signal; obtaining time-frequency feature maps of at least two electrode signals in the first EEG signal; performing feature extraction based on the time-frequency feature maps of the at least two electrode signals to obtain a first extracted feature map; performing weighting processing based on an attention mechanism on the first extracted feature map to obtain an attention feature map; and obtaining a motor imagery type of the first EEG signal based on the attention feature map.

Abstract: A system and method for efficient data storage, transfer, synchronization, and security using automated model monitoring and training. The system analyzes test datasets to detect data drift, retraining encoding and decoding algorithms as needed. New data sourceblocks are created and assigned codewords, compiling an updated codebook for distribution to connected devices. A novel dyadic distribution subsystem simultaneously compresses and encrypts data by transforming input streams into a dyadic distribution. This process generates a compressed main data stream and a secondary stream of transformation information, which are combined into a secure output. The system includes a network device manager for optimizing codebook distribution based on device resource usage. Operating in both lossless and lossy modes, the system offers flexible, efficient, and secure data handling across various network configurations.

Abstract: A system and methods for bandwidth-efficient data encoding comprising a sequence analyzer configured to: analyze a received sequence dataset to determine a sequence dataset file type, scan the sequence dataset to maintain a count of unique characters contained therein, identify positions where the unique character count increases by a power of two, deconstruct the sequence dataset into a plurality of sourceblocks at the identified positions, and encode the plurality of sourceblocks using a data deconstruction engine and library management module to assign each sourceblock a reference code.

Abstract: Methods, systems, and devices for validity mapping techniques are described. A memory device may use a change log to update a mapping that indicates whether data stored at respective physical addresses is valid. For example, the memory device may receive a command associated with data having a corresponding set of addresses (whether logical block addresses or physical addresses). The memory device may set an entry of the change log based on whether the set of addresses are consecutive. For example, the memory device may identify whether the set of addresses are consecutive and may set a flag in the entry of the change log to indicate whether the addresses are consecutive. Then, the memory device may update one or more entries of the mapping corresponding to the entry of the change log to indicate whether the addresses corresponding to the one or more entries of the mapping store valid data.

Abstract: A system and method for securing high-speed communications between processing units on computer chips, wherein a training data set is used to find patterns and associated smaller indices, or codewords, which are stored in a reference codebook library, and where reconstruction and deconstruction algorithms are used to encode and decode data as it is received. The codebook and algorithms may be stored in the firmware of a semiconductor which enable reduced resources and cost when transmitting data between or among devices that utilize such semiconductors.

Abstract: A method by which an electronic device performs a DNN operation includes performing a first modified operation including extending a channel of an output of a first layer with respect to a feature map input into the first layer, the first layer being one of a plurality of layers of a DNN, wherein the first modified operation includes a space-to-depth transformation operation, performing a neural network operation corresponding to layers between the first layer and a second layer as a channel-extended neural network operation, wherein the second layer is a layer of the plurality of layers of the DNN after the first layer, performing a second modified operation including reducing a channel of an output of the second layer with respect to a channel-extended feature map input into the second layer, wherein the second modified operation includes a depth-to-space transformation operation, and outputting a result of the DNN operation.