Abstract: A storage device a nonvolatile memory device that stores or read data, and a controller that controls the nonvolatile memory device based on a first physical address of the nonvolatile memory device and performs a data input/output request from a host. The controller generates the first physical address based on bit information being bits at a preset bit position in a logical address associated with the data input/output request and based on a second physical address of the nonvolatile memory device stored in a mapping table. The mapping table includes information about a correlation of the logical address and the second physical address.

Abstract: Methods, systems, and devices for logical-to-physical (L2P) mapping for zoned namespace (ZNS) memory systems are described. A memory system may include a cache, such as a single-level cell (SLC) cache in front of a quad-level cell (QLC) non-volatile memory device. The cache may include a multiple layer L2P table to map logical block addresses (LBAs) of data to physical addresses of the cache. In some examples, the L2P table may be sparsely populated to hold a quantity of LBAs corresponding to a quantity of open zones, and may be organized into groups of L2P entries to address a full logical space of the memory device. L2 Region boundaries may be aligned on zone boundaries by utilizing an integer quantity of L2 regions for each zone, an integer quantity of L2P entries per L2 region, or both, to reduce complexity and write amplification while improving performance.

Abstract: A method includes determining a health characteristic value of a block of memory cells, determining a difference between the health characteristic value and a health threshold, determining, based on the difference, a weight to associate with a block of memory cells, selecting, based on the weight, a block of memory cells for a media management operation; and performing a media management operation on the selected block of memory cells.

Abstract: The present disclosure includes apparatuses and methods for simultaneous in data path compute operations. An apparatus can include a memory device having an array of memory cells and sensing circuitry selectably coupled to the array. A plurality of shared I/O lines can be configured to move data from the array of memory cells to a first portion of logic stripes and a second portion of logic stripes for in data path compute operations associated with the array. The first portion of logic stripes can perform a first number of operations on a first portion of data moved from the array of memory cells to the first portion of logic stripes while the second portion of logic stripes perform a second number of operations on a second portion of data moved from the array of memory cells to the second portion of logic stripes during a first time period.

Abstract: Solid State Drive (SSD) devices with hardware accelerators and methods for apportioning storage resources in the SSD are disclosed. SSDs typically comprise an array of non-volatile memory devices and a controller which manages access to the memory devices. The controller may also comprise one or more accelerators to either improve the performance of the SSD itself or to offload specialized computation workloads of a host-computing device. Different accelerators may be dynamically assigned portions of the non-volatile memory array according to the type of data being accessed and/or the throughput required. Provision is also made for the data to be accessed directly by the accelerators bypassing the controller and for a hinting mechanism to improve accelerator performance.

Abstract: Methods, systems, and devices for data relocation scheme selection for a memory system are described. A system may select, based on a fragmentation characteristic of data associated with a block of addresses, whether to perform a relocation associated with relocating invalid data, or to perform a relocation associated with refraining from relocating invalid data. A relocation associated with relocating invalid data may be selected for relatively more-fragmented data, which may avoid a relatively higher latency or processing load associated with evaluating validity or updating logical-to-physical mapping at a more-granular level.

Abstract: A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.

Abstract: A system and method for multi-level compaction of floating-point numbers and associated metadata within datasets. The system identifies floating-point numbers and their associated metadata, pre-encodes numbers into binary string representations, and encodes metadata into compact binary form. These encoded elements are linked together and indexed to indicate they represent floating-point numbers with metadata. The dataset is organized into multiple compaction levels based on semantic relationships between metadata elements. The system creates specialized indices for metadata-based retrieval, maintains relationship maps, and implements inheritance policies across hierarchical levels. During retrieval, the system reconstructs both the original floating-point values and their associated metadata, preserving hierarchical relationships.

Abstract: A computer system with a central, non-system memory (NSM) gateway circuit for routing non-DRAM transactions between agent circuits coupled to a plurality of networks of the computer system, which may include packet-switching capabilities. Such non-DRAM transactions may be routed via a virtual channel in some implementations. To facilitate handling of such transactions, the NSM gateway circuit may include dedicated routing storage (e.g., an input buffer for each source agent circuit on each of the plurality of networks and an output buffer for each destination agent circuit on each of the plurality of networks). The NSM gateway circuit may serve as a termination point for non-DRAM transactions within the computer system, allowing network credit for a message included in a non-DRAM transaction to be returned to a source agent circuit prior to delivery to one or more destination agent circuits.

Abstract: A memory controller comprises a command interface to transmit a memory command to a plurality of memory devices associated with the memory controller. The memory controller also comprises an acknowledgement interface to receive an acknowledgment status packet from the plurality of memory devices over a shared acknowledgement link coupled between the memory controller and the plurality of memory devices, the acknowledgement status packet indicating whether the command was received by the plurality of memory devices. In addition, the memory controller comprises a memory controller core to decode the acknowledgment status packet to identify a portion of the acknowledgement status packet corresponding to each of the plurality of memory devices.

Abstract: Devices, methods, and systems for shutdown and restart management in a distributed computing environment are described herein. One method includes determining whether a backup of a workload in a distributed computing environment exists, causing a shutdown sequence of the workload to occur at a first predetermined time to shut down the workload, and causing a restart sequence of the workload to occur to restart the workload in the distributed computing environment.

Abstract: A host system is coupled to a storage device and manages completion queues (CQs) for the storage device. The host system includes a host controller and memory that stores submission queues (SQs) and the CQs. The host controller fetches a command from a given SQ that corresponds to a target CQ. The host controller saves the command in an SQ internal buffer of the host controller, calculates an available capacity (AC) associated with the given SQ for the host system to store a response to the command from the storage device, and sends the command to the storage device when the available capacity is non-zero. The available capacity is calculated based on, at least in part, available slots in the target CQ.

Abstract: An information processing apparatus including a plurality of components, includes: a power circuit unit capable of switching between supplying and stopping operating power to the plurality of components; a first component of the plurality of components, the first component being related to external power supply, and being supplied with operating power directly from the power circuit unit; a second component of the plurality of components, the second component being not related to the external power supply; a switch unit connected between the power circuit unit and the second component, the switch unit being capable of switching between supplying and stopping the operating power supplied from the power circuit unit to the second component; and a sub-controller that is operable with power supply to a main controller stopped, the main controller executing information processing based on an operating system (OS).

Abstract: Garbage collection technology for non-volatile memory is shown. Space allocation of the non-volatile memory is presented by a plurality of logical-to-physical address mapping sub-tables. The processor selects a plurality of source blocks and a destination block from the non-volatile memory for garbage collection. In order from the lowest to the highest logical address, the processor selects the logical-to-physical address mapping sub-tables in turn for use as a scan target, to perform a full scan of each logical-to-physical address mapping sub-table. In this way it identifies valid data in the source blocks, collects the valid data obtained from the source blocks, and programs the valid data to the destination block.

Abstract: A method includes: generating a first sum value at least by a first resistor; generating a first shifted sum value based on the first sum value and a nonlinear function; generating a pulse number based on the first shifted sum value; and changing the first resistor based on the pulse number to adjust the first sum value.

Abstract: A memory read response is received from a memory controller in response to a memory request and includes specific data and specific metadata attendant to the specific data retrieved with specific memory addresses in the device memory. The specific data and specific metadata are sent to a host device in a host-bound memory read response. In response to determining that a metadata update condition is satisfied, a number of actions are performed as follows. Specific modified metadata attendant to the specific data is determined. A MEMC-bound memory write request for metadata update is generated. The MEMC-bound memory write request is used to write the specific modified metadata attendant to the specific data in the device memory. The specific data and the specific modified metadata are stored in an entry of a temporary write buffer until the entry is invalidated by the corresponding metadata update write acknowledgement returned from the MEMC.

Abstract: An apparatus comprises at least one processing device configured to determine, for a given portion of data to be replicated from a first multiple-tier storage system to a second multiple-tier storage system, tiering information characterizing a given storage tier of the first storage system in which the given portion of data is stored. The at least one processing device is also configured to select, based at least in part on the determined tiering information and storage tier mapping policies mapping storage tiers between the first and second multiple-tier storage systems, one of the storage tiers in the second multiple-tier storage system. The at least one processing device is further configured to replicate the given portion of data from the given storage tier of the first multiple-tier storage system to the selected storage tier of the second multiple-tier storage system.

Abstract: Examples of the present disclosure provide a memory system and operation method thereof, a memory device and operation method thereof. In one example, the operation method for the memory system includes: obtaining a wear value of a system area and a wear value of a user area within a first period of time; and determining whether to reallocate virtual blocks in a first reserved area of the system area and a second reserved area of the user area based on a result of comparison between the wear value of the system area and the wear value of the user area. Other examples are shown and described.

Abstract: A method of circuit conception of a computational memory circuit including a memory having memory cells, the method including: receiving an indication of the memory storage size and an indication of an instruction frequency of the instructions to be executed by the computational memory circuit; evaluating for a plurality of candidate types of memory cells, a number representing an average number of cycles of the memory of the computational memory circuit per instruction to be executed; determining, for each of the plurality of candidate types of memory cells, a minimum operating frequency of the computational memory circuit based on the number N and on the memory storage size; selecting one of the plurality of candidate types of memory cells based on the determined minimum operating frequency; and performing the circuit conception based on the selected type of candidate memory cell.

Abstract: The description relates to adaptive data storage management. An example manages data within a database system using dynamically adjustable mini-pages within a buffer pool. The example involves receiving a request for a data item, adjusting mini-page sizes based on the request, and determining the data item's presence within these mini-pages. Upon locating the item, the request is executed on the relevant mini-page. The example also updates a mapping table to correlate mini-page identifiers with their locations in the database, and selectively caches or evicts the data item based on probabilities and access patterns.