Patents Examined by Michael B Shingleton
  • Patent number: 8134415
    Abstract: Electronic circuitry comprising operational circuits of active switching type requiring timing signals, and conductive means for distributing said timing signals to the operational circuits, wherein the timing signal distribution means includes a signal path that has different phases of a drive signal are supplied via active means at different positions about the signal path where that path exhibits endless electro-magnetic continuity without signal phase inversion or has interconnections with another signal path having different substantially unidirectional signal flow where there is no endless electromagnetic continuity between those signal paths and generally has non-linear associated circuit means where the signal path is of a transmission line nature.
    Type: Grant
    Filed: November 8, 2009
    Date of Patent: March 13, 2012
    Assignee: Multigig, Inc.
    Inventor: John Wood
  • Patent number: 8067803
    Abstract: A memory device and method of making the memory device. The memory device comprises a storage transistor at a surface of a substrate. The storage transistor comprises a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line is connected to the gate structure.
    Type: Grant
    Filed: October 16, 2008
    Date of Patent: November 29, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Chandra V. Mouli, Gurtej S. Sandhu
  • Patent number: 8058694
    Abstract: In a semiconductor device, such as a MOSFET or the like, which is a high-frequency LSI achieving a low noise figure and a high maximum oscillation frequency and which has unit cells with a ring-shaped gate electrode arranged in an array, gate drawing wires connecting together the gate electrode and gate contact pad portions are arranged on a region excluding a drain region and a source region, that is, on an isolation region. Bending portions of the ring-shaped gate electrode are all formed on the isolation region. This therefore permits an improvement in high frequency characteristics such as noise, the maximum oscillation frequency, and the like while eliminating unnecessary gate capacity addition, and also permits small characteristic variation even if a machining shape of the bending portions of the gate electrode is unstable.
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: November 15, 2011
    Assignee: Panasonic Corporation
    Inventor: Hiroshi Shimomura
  • Patent number: 8040180
    Abstract: An operational amplifier capable of compensating offset voltage includes an input stage circuit having a positive input end, a negative input end, a first current output end, and a second current output end, for outputting current corresponding to voltage received by the positive and negative input ends, an output stage circuit coupled to the first current output end and the second current output end of the input stage circuit, for outputting voltage according to current outputted from the first current output end and the second current output end, and an trimming device coupled between the input stage circuit and the output stage circuit, for adjusting current of the first current output end or the second current output end for compensating offset voltage.
    Type: Grant
    Filed: July 5, 2007
    Date of Patent: October 18, 2011
    Assignee: NOVATEK Microelectronics Corp.
    Inventors: Chih-Jen Yen, Chih-Yuan Hsieh
  • Patent number: 8035446
    Abstract: A digital signal processor includes an up-sampling module that samples an input signal and generates up-sampling points. A natural sampling module includes a reference signal generation module that generates a reference signal. A crossing point detection module receives the up-sampling points and the reference signal and uses interpolation to detect intersection points of the input signal and the reference signal. The crossing point detection module determines values of the input signal at first and second evaluation times. The crossing point detection module estimates a current intersection point of the input signal and the reference signal as an intersection of the reference signal and a line that extends between first and second points on the input signal that correspond with the first and second evaluation times. A frequency of the reference signal is variable and a current switching period of the reference signal is not equal to a previous switching period.
    Type: Grant
    Filed: April 19, 2005
    Date of Patent: October 11, 2011
    Assignee: Marvell International Ltd.
    Inventors: Zhipei Chi, Peiqi Xuan, Runsheng He
  • Patent number: 8013370
    Abstract: A solid-state imaging device has a substrate in which are formed a pixel array portion having a plurality of pixels, and a peripheral circuitry portion. The device is characterized in that a first multilevel metallization structure is formed over the peripheral circuitry portion, and a second multilevel metallization structure thinner than the first multilevel metallization structure is formed over the pixel array portion.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: September 6, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroshi Kobayashi, Katsuyoshi Yamamoto, Tadao Inoue, Toshitaka Mizuguchi
  • Patent number: 7999613
    Abstract: An amplifier system is provided that has a first balun with an input and an output, and a second balun with an input and an output. A first set of amplifiers is coupled in series and to the output of the first balun. A second set of amplifiers is coupled in series and to the output of the second balun. The first and second sets of amplifiers are in series or parallel. A load impedance of the first and second sets of amplifiers does not substantially change at an output of any amplifier that is switched on when another amplifier is switched off.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: August 16, 2011
    Assignee: Amalfi Semiconductor, Inc.
    Inventors: Lawrence Burns, Chong Woo, Wendell Sander
  • Patent number: 7999284
    Abstract: A solid-state imaging device 1 is arranged so that a hollow section 9 is formed between a solid-state imaging element 2 and a covering section 4 and an air path 7 is formed in an adhesive section 5 so as to extend from the hollow section 9 to the outside, wherein the adhesive section 5 is formed so as not to be positioned on a signal processing section 8 for processing a signal of the solid-state imaging element 2. This makes it possible to reduce noises occurring in the signal processing section of the semiconductor element while preventing occurrence of condensation in the covering section for covering the semiconductor element.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: August 16, 2011
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kiyoshi Kumata, Kazuya Fujita
  • Patent number: 7994414
    Abstract: A semiconductor device is disclosed that can operate utilizing thermoelectric concepts. According to an embodiment, the semiconductor device can comprise: a source/drain conductor formed of a line of metal material on a substrate; a first gate conductor formed of a second line of metal material; and a second gate conductor formed of a third line of metal material, wherein the first gate conductor is disposed adjacent a first portion of the source/drain conductor at one end of the source/drain conductor and the second gate conductor is disposed spaced apart from the first gate conductor and adjacent a second portion of the source/drain conductor at the other end of the source/drain conductor. By applying current to the first gate conductor and the second gate conductor, current can be supplied from the one end of the source/drain conductor to the other end of the source/drain conductor.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: August 9, 2011
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Myung Soo Kim
  • Patent number: 7956691
    Abstract: A system and method for over-voltage protection of a power amplifier is provided. A power amplifier is typically employed in a transmitter to amplify signals prior to transmission via a load; the load may include an antenna or a cable. As a result of an impedance mismatch between the power amplifier and its load, excess power from the power amplifier output fails to reach the load and must be dissipated by one or more transistors in the power amplifier. In severe impedance mismatch conditions, this dissipated power may damage or destroy the transistor(s). An automatic gain control (AGC) is provided for detecting a gain difference between the power amplifier and a replica power amplifier. A gain difference may signal an over-voltage situation. The AGC may be configured to adjust the gain of the power amplifier if a gain difference exists to prevent device damage.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: June 7, 2011
    Assignee: Broadcom Corporation
    Inventors: Ramon Gomez, Flavio Avanzo, Giuseppe Cusmai, Takayuki Hayashi
  • Patent number: 7952427
    Abstract: A signal amplifier circuit includes peak value holding circuit 11 receiving positive-phase input signal, peak value holding circuit 12 receiving negative-phase input signal, adder 13 adding the positive-phase input signal and output signal of peak value holding circuit 12, adder 14 adding the negative-phase input signal and output signal of the peak value holding circuit 11, non-inverting amplifier 15 amplifying output signal of adder 13, non-inverting amplifier 16 amplifying output signal of adder 14, peak value holding circuit 21 receiving positive-phase output signal of non-inverting amplifier 15, peak value holding circuit 22 receiving negative-phase output signal of non-inverting amplifier 16, adder 23 adding the positive-phase output signal and output signal of peak value holding circuit 22, adder 24 adding the negative-phase output signal and output signal of peak value holding circuit 21, and differential amplifier 29 amplifying difference between output signals of adders 23 and 24.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: May 31, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Takeshi Nagahori
  • Patent number: 7940120
    Abstract: The power amplifier mainly includes a main amplifier, two splitters, one combiner, one subtracter, two phase shifters, one attenuator and one error amplifier. The splitters, subtracter and combiner are designed in the form of 90-degree or quadrature hybrid couplers. A quadrature hybrid can be implemented with any lumped or transmission-line elements and has an important advantage compared to the in-phase splitter that at equal values of reflection coefficients from loads connected to the in phase and 90° phase shift terminals, the reflection wave is lacking at the main input terminal and, consequently, the input voltage standing wave ratio of a quadrature hybrid does not depend on the equal load mismatch level.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: May 10, 2011
    Assignee: Alcatel Lucent
    Inventors: Andrei Grebennikov, Florian Pivit
  • Patent number: 7940381
    Abstract: A semiconductor nanowire is coated with a chemical coating layer that selectively attaches to the semiconductor material and which forms a dye in a chemical reaction. The dye layer comprises a material that absorbs electromagnetic radiation. A portion of the absorbed energy induces electronic excitation in the chemical coating layer from which additional free charge carriers are temporarily donated into the semiconductor nanowire. Thus, the conductivity of the semiconductor nanowire increases upon illumination on the dye layer. The semiconductor nanowire, and the resulting dye layer collective operate as a detector for electromagnetic radiation.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: May 10, 2011
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Lidija Sekaric
  • Patent number: 7936211
    Abstract: Controlling the performance of the thermionic tube (102) having a cathode (103), a plate (104) and a grid (105) is disclosed. The tube is configured to provide amplification of an audio derived signal (106) and is arranged to apply a grid bias voltage to the grid. The absence of an input audio signal is detected whereafter output current between cathode and plate is measured to identify actual output current. The actual output current is compared against a preferred output current and the grid bias voltage is adjusted so as to bring the actual output current value towards the preferred output current value.
    Type: Grant
    Filed: August 6, 2009
    Date of Patent: May 3, 2011
    Assignee: KBO Dynamics International Limited
    Inventors: Colin Arrowsmith, Andrew Fallon
  • Patent number: 7935990
    Abstract: A method and apparatus is provided for use in power amplifiers for reducing the peak voltage that transistors are subjected to. A power amplifier is provided with first and second switching devices and an inductor connected between the switching devices. The switching devices are driven such that the switching devices are turned on and off during the same time intervals.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: May 3, 2011
    Assignee: Black Sand Technologies, Inc.
    Inventors: Susanne A. Paul, Timothy J. Dupuis, John Blake Pavelka
  • Patent number: 7932574
    Abstract: A solid-state imaging device having a light receiving section comprised of a stack of a photoconductive layer for absorbing light in a wavelength region for red, a photoconductive layer for absorbing light in a wavelength region for green, and a photoconductive layer for absorbing light in a wavelength region for blue. A transparent electrode layer is provided preferably above each of the photoconductive layers and a translucent reflective layer for reflecting light in a desired wavelength is provided.
    Type: Grant
    Filed: May 4, 2004
    Date of Patent: April 26, 2011
    Assignee: Sony Corporation
    Inventor: Hideo Kanbe
  • Patent number: 7932777
    Abstract: A switching amplifier drives balanced piezoelectric or other capacitive or reactive loads with a minimum physical electronics volume, enabling a compact arrangement that can combine amplifier and transducer at the same physical location. Power supply current is minimized by using two or more transducers driven with phase-shifted signals, resulting in stored energy being cycled between the transducers rather than being carried over the power supply lines for storage in a power supply. Auxiliary power supply capacitors to store energy coming out of the load can thus be minimized. The modulation scheme puts the switching frequencies in common-mode while the baseband signals are differential mode. The common-mode switching frequency signals are blocked from the loads by a common-mode inductor. The common-mode inductor can be physically small as a result of the large baseband load currents being in differential mode.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: April 26, 2011
    Inventors: George Gustave Zipfel, Jr., Christie Lewis Zipfel
  • Patent number: 7924098
    Abstract: A first FET is inserted in a series position between a signal input terminal and a signal output terminal, while second and third FETs are inserted in a shunt position respectively between the signal input terminal and a ground terminal and between the signal output terminal and a ground terminal. First and second reference voltage terminals and a control terminal are provided. A first reference voltage and a control voltage are applied to the first FET, while a second reference voltage and a control voltage are applied respectively to the second and third FETs, so that the first, second, and third FETs serve as variable resistors. As such, a gain control circuit is constructed. Further, a first resistor is provided in parallel to the first FET, while second and third resistors are provided respectively in series to the second and third FETs.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: April 12, 2011
    Assignee: Panasonic Corporation
    Inventors: Masao Nakayama, Tsunehiro Takagi, Masahiko Inamori, Kaname Motoyoshi
  • Patent number: 7920022
    Abstract: A switched capacitor system with output glitch reduction step charges the switched capacitor by switching it to a first voltage level in a first phase, to an intermediate voltage level of a pre-charge node in a pre-charge phase and to the voltage level of the output node of the amplifier stage in a settling phase; the pre-charge node can be implemented at the input of the amplifier stage, the output of a preceding stage or at any other pre-existing suitable node in the amplifier system.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: April 5, 2011
    Assignee: Analog Devices, Inc.
    Inventor: Olafur Mar Josefsson
  • Patent number: 7915954
    Abstract: Methods and apparatus for amplifier AM and PM predistortion and autocalibration. AM and PM amplifier distortion can be corrected using predistortion. The AM and PM distortion characteristics of the amplifier are determined using an autocalibration technique. The amplifier characteristics can be stored in distinct look up tables. Alternatively, the inverse of the amplifier characteristics can be stored in distinct look up tables. Signals that are to be amplified are characterized in polar format having a phase component with a normalized magnitude and a magnitude component. The phase component can be predistorted by applying the inverse of the PM distortion characteristics to the signal. Similarly, the magnitude component can be predistorted by applying the inverse of the AM distortion characteristics to the signal. The predistorted phase component can be amplified using the previously characterized amplifier.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: March 29, 2011
    Assignee: QUALCOMM, Incorporated
    Inventors: Arun Raghupathy, Puay Hoe See, Gurkanwal Kamal Sahota, Robert Reeves, Paul E. Peterzell