Patents Examined by Michael C. Sachs
  • Patent number: 4089028
    Abstract: A first set of digital signals is generated in response to information received from a magnetic tape. The first set of digital signals is stored. A second set of digital signals is generated in response to the first set of stored signals and information received from a punched tape. The second set of digital signals is stored. One or more external devices or peripheral control equipment connected to a plurality of external devices is controlled in response to the second set of stored signals. The second set of stored signals is transmitted in a form for storage on the magnetic tape or the punched tape.
    Type: Grant
    Filed: March 20, 1975
    Date of Patent: May 9, 1978
    Assignee: United Audio Visual Corporation
    Inventor: William R. Wells
  • Patent number: 4004278
    Abstract: In a virtual memory system capable of embodying therein multiple virtual spaces used in a switching mode and having a high speed memory for storing address sets each including a virtual address of the virtual space and a real address of a real space corresponding to the virtual address and indicators for setting the validity or invalidity state of the corresponding address sets, a switching system such that when the multiple virtual spaces are switched, the virtual address in the addressed address set is compared with a special address stored in a register by a comparator, and the indicator corresponding to the addressed address set is set to the invalidity state when the result of comparison fulfills a predetermined condition.
    Type: Grant
    Filed: March 18, 1974
    Date of Patent: January 18, 1977
    Assignee: Hitachi, Ltd.
    Inventor: Shigeo Nagashima
  • Patent number: 3970994
    Abstract: A communication switching system having distributed control and modular design including a loop structure to which processor modules and storage modules are attached. Input to and output from the loop are effected through line registers, one line register being provided for each communication line. The line registers also function as intermediate storage between sequential processing steps. The processor modules, which are physically separated from the storage modules, are allocated for each step of a task, completely independent of the communication line associated with that task, or any past allocation of that task. Accordingly, messages can be sent by a processor module to any one of the storage modules for fetching or delivering of data and then the data will be routed back to the processor modules. After all required processing has been accomplished, a message will be sent back to the associated line register containing new data, either for output to the line or for later reuse by the system.
    Type: Grant
    Filed: February 28, 1974
    Date of Patent: July 20, 1976
    Assignee: International Business Machines Corporation
    Inventor: Christian Jakob Jenny
  • Patent number: 3969702
    Abstract: A data processing system includes a control unit, working store and an operating section for performing operations upon information fetched from the working store. The operating section includes a plurality of independent, functionally different units. The control unit during the fetching and execution of program instructions enables a number of the units to perform different operations simultaneously upon the same information thereby increasing the overall speed of processing program instructions.
    Type: Grant
    Filed: July 2, 1974
    Date of Patent: July 13, 1976
    Assignee: Honeywell Information Systems, Inc.
    Inventor: Giancarlo Tessera
  • Patent number: 3967247
    Abstract: A storage interface unit adapted to serve as a high speed buffer between plural requestor units and a relatively low speed main memory in a data processing system. The high speed buffer provides temporary storage for a limited number of blocks of data stored in the main memory. When a particular address is requested by a requestor unit, a check is made to determine if that address is resident in the high speed buffer and if so, it is available to the requestor unit for reading or writing. If the desired address is not resident in the high speed buffer, a block in the buffer is selected for replacement. In accordance with the present invention, when a block is to be displaced from the buffer and a new block is requested from the main memory, during the interval that the new block is requested from the main memory, the block to be displaced is checked for modifications.
    Type: Grant
    Filed: November 11, 1974
    Date of Patent: June 29, 1976
    Assignee: Sperry Rand Corporation
    Inventors: Vernon K. Andersen, Michael W. Goddard
  • Patent number: 3965457
    Abstract: A digital control processor for controlling a number of relay sets from digital information received from a digital PABX. The digital control processor consists essentially of a first-in first-out memory and a combinational logic unit. The memory stores information relevant to an operation to be performed by the processor and re-cycles the information until the operation has been performed. The memory determines the action of the combinational logic unit which action includes changing the state of one of the relay sets. The action of the combinational logic unit is determined by time varying data states from the memory and/or from a relay set or sets. The digital control processor acts as an interface device between the digital/electronic world of the PABX and the analogue/mechanical world of the public exchange. The device receives digital information from a processor in the PABX and also monitors the current state of all the relay sets.
    Type: Grant
    Filed: November 13, 1973
    Date of Patent: June 22, 1976
    Assignee: L.M. Ericsson Pty. Ltd.
    Inventor: Keith Harwood
  • Patent number: 3961170
    Abstract: In a digital electronic computer which comprises a memory including a first and a second register, the first register is receptive of a number to be converted from fixed to floating point notation and the second register is receptive of a significant zero digit with an associated decimal point. Shifting means including a register is operable to shift the contents of either register and aligning means is operable to cause shifting of the second register until the decimal point stored therein is aligned with the decimal point in the first register. Indicating means indicates whether the number stored in the first register is greater or less than one and the shifting means next begins shifting the contents of one or the other of the registers when the number is indicated greater or less than one respectively.
    Type: Grant
    Filed: April 17, 1974
    Date of Patent: June 1, 1976
    Assignee: Ing. C. Olivetti & C., S.p.A.
    Inventors: Giovanni De Sandre, Angelo Subrizi, Franco Bretti
  • Patent number: 3958223
    Abstract: Disclosed is an expandable calculator system of the type implemented on semiconductor chips and featuring additional data storage registers for increasing data storage capacity of the basic system. A basic calculator system comprising two semiconductor chips is provided with additional semiconductor chips each providing a plurality of separately addressable registers for storing data, to thereby increase the data storage capacity of the two-chip system. Ten registers are desirably provided per external chip, and a novel method of addressing particular external register chips and particular registers therein is utilized. First and second signals synchronize the internal timing of the external register chips and also enable communication to the external chips. After the external register chip has been enabled, the appropriate memory is addressed via the same lines on which the data is subsequently transmitted to the memory.
    Type: Grant
    Filed: July 28, 1975
    Date of Patent: May 18, 1976
    Assignee: Texas Instruments Incorporated
    Inventor: Michael J. Cochran
  • Patent number: 3958225
    Abstract: A communications terminal control circuit is described which includes a preprogrammed memory. The memory provides a plurality of sequential instruction signals each serving to direct at least a selected operational sequence of the terminal. Two command and two status decoders are included, each responsive to at least one of the instructional signals and capable of initiating a unique terminal operation in response to a selected instructional signal from the memory. Means are provided for comparing outgoing and incoming coded information with selected memory locations thereby analyzing such coded information and directing selected operative terminal instructions in response thereto.
    Type: Grant
    Filed: January 28, 1974
    Date of Patent: May 18, 1976
    Assignee: Teletype Corporation
    Inventors: Kenneth W. Turner, George C. Zobel
  • Patent number: 3958221
    Abstract: This invention relates to a method and apparatus for determining the address mode of each instruction in a microprogrammed processor, and for utilizing the address mode determination to locate the effective operand of the instruction. A microprogram memory is included which contains microprogram micro-orders for controlling the obtaining of the effective operand for an instruction in each of the address modes. The address being accessed in the microprogram memory at any given time is stored in a microprogram register. There is a decoder which is operative in response to the address mode tag of an instruction for generating the address of the entry point in the microprogram memory for the microprogram micro-orders to be utilized to control the obtaining of the effective operand for the mode indicated by the tag. The address mode tag of each instruction is applied to the decoder and the microprogram entry point address read out from the decoder in response to the tag is stored in the microprogram register.
    Type: Grant
    Filed: June 7, 1973
    Date of Patent: May 18, 1976
    Assignee: Bunker Ramo Corporation
    Inventors: John J. Serra, Ronald T. Prodan
  • Patent number: 3950730
    Abstract: Apparatus and process for the rapid processing of the data in a data processing system having a segmented memory, wherein descriptors representing the characteristics of the segments are employed in retrieving from memory and processing each segment, and wherein means is provided for the rapid locating of the descriptors for the segments most frequently utilized.
    Type: Grant
    Filed: September 19, 1973
    Date of Patent: April 13, 1976
    Assignee: Compagnie Honeywell Bull (Societe Anonyme)
    Inventors: Jacques Michel Jean Bienvenu, Michel Lecuyer
  • Patent number: 3947663
    Abstract: A device for reading from and writing on, magnetic cards for use in a desk-top computer having a cover with an introduction slot and an exit slot for the cards. The device comprises two parallel guides between the introduction and exit slots for defining the path to be traversed by the cards, two support plates for the guides disposed perpendicular thereto for guiding the lateral edges of the cards and a belt cooperating with pressure rollers to entrain the card as it passes through the guides. The device also includes a microswitch and a shoe which has two projections contacting the non-magnetizable face of the card, the shoe being hinged on a lever actuating the microswitch when the card has passed below the projections.
    Type: Grant
    Filed: April 17, 1974
    Date of Patent: March 30, 1976
    Assignee: Ing. C. Olivetti & C., S.p.A.
    Inventors: Giovanni De Sandre, Angelo Subrizi, Franco Bretti
  • Patent number: 3944983
    Abstract: Disclosed is an expandable calculator system of the type implemented on semiconductor chips providing additional data storage registers for increasing data storage capacity of the basic system. A basic calculator system comprising two semiconductor chips is provided with additional semiconductor chips each providing a plurality of separately addressable registers for storing data, to thereby increase the data storage capacity of the two-chip system. First and second control signals synchronize the internal timing of the external register chips and also enable communication to the external chips. The data system has 10 registers which are addressed by means responsive to instructions communicated via the data transmission path. A first set of data word digits is read into the appropriate memory, then right shifted, and then another set of data word digits are read in. Means are provided for clearing all registers on one chip of the internal register chip set.
    Type: Grant
    Filed: June 11, 1973
    Date of Patent: March 16, 1976
    Assignee: Texas Instruments Incorporated
    Inventor: Pliny M. Gale
  • Patent number: 3942156
    Abstract: Circuits for the improved operation of microprogrammable computers are described. This improvement is accomplished by providing a set of read-only memory devices for storing the micro-code for all combinations of arithmetic logic unit function, carry bit and file register address than can be specified by an instruction word executed from Main Memory. In a universal microprogram designed to execute that family of Main Memory instructions that differ only in the functions specified above, the instruction word is used to address the read-only memory devices, the micro-code output of which is used to control the file, carry in bit and arithmetic logic unit. Through the use of these circuits a family of instructions may be executed by a single microprogram and at no increase in execution time over that required for the execution of a microprogram dedicated to a single instruction.
    Type: Grant
    Filed: December 17, 1973
    Date of Patent: March 2, 1976
    Assignee: Xerox Corporation
    Inventors: Howard C. Mock, Kenneth N. Isaac, Charles P. Disparte, Warren L. Hall
  • Patent number: 3938073
    Abstract: This abstract describes a system for the field recording of seismic data in which a large plurality of geophones are divided into groups and each group is connected to an array terminal. All of the array terminals are connected in series, by cables, with the last terminal connected to a recording unit. In each of the terminals there are means to process the geophone analog signals by amplifying and adding them to a selected shifting function, and axis-crossing-coding (AXC) the resulting sum signals to provide a plurality of pulses which are stored in a prallel-to-serial converter. In addition, each of the terminals contains a buffer register.
    Type: Grant
    Filed: March 28, 1975
    Date of Patent: February 10, 1976
    Assignee: Geophysical Systems Corporation
    Inventors: J. Robert Fort, James A. Westphal, Donald R. Juilfs
  • Patent number: 3938097
    Abstract: Random access storage facilities for the CPU of a computer are cascaded in that a facility of relatively fast access speed holds a subset of information held in a facility of lower speed. Memory read requests are applied sequentially to these storage facilities, beginning always with the one of highest access speed, while requests satisfied by a lower speed facilities lead to storage of that information in all facilities of higher access speed. Write requests are made only to one facilities of lower speed, with algorthmic updating of the facility of lowest speed while the ones of higher speed are updated only on subsequent read requests for the same location. The several facilities which can be updated make storage space available on the basis of usages.
    Type: Grant
    Filed: April 1, 1974
    Date of Patent: February 10, 1976
    Assignee: Xerox Corporation
    Inventor: Reaman Paul Niguette, III
  • Patent number: 3936803
    Abstract: A data processing system where transfers of information are made between I/O devices and system storage through channels is a channel unit having common apparatus shared among all the channels. The common apparatus includes a sequentially accessed state memory and a plurality of processors. The state memory includes a memory location for each channel. The processors have access to different parts of the state memory and perform functions in response to stored information. A data access processor controls transfers between system storage and the channel unit. A controller interface processor controls transfers between the channel unit and I/O devices. The quantity of information to be transferred for each channel is stored in the state memory. Each time a portion of the total transfer is completed, a count field in the state memory is updated.
    Type: Grant
    Filed: November 19, 1973
    Date of Patent: February 3, 1976
    Assignee: Amdahl Corporation
    Inventors: James A. Katzman, Yoshiro Yoshioka
  • Patent number: 3936806
    Abstract: The invention relates to a unique solid state computer organization. Essentially, the system comprises a plurality of associative arrays wherein each associative array comprises parallel processing apparatus and a solid state memory capable of being accessed in either a word-oriented or a bit-oriented mode. The associative processor apparatus within each associative array provides for the parallel processing of data within the associative arrays in either of the two modes. Control apparatus within the system provides for the parallel control of the plurality of associative arrays at a speed conducive to the data processing speed of the associative arrays. Rapid speed of the control apparatus is economically achieved by the arrangement of a plurality of separate and characteristically distinct control memory elements.
    Type: Grant
    Filed: April 1, 1974
    Date of Patent: February 3, 1976
    Assignee: Goodyear Aerospace Corporation
    Inventor: Kenneth E. Batcher
  • Patent number: 3934230
    Abstract: Automatic selector for peripheral equipment capable of operating alternately with one or the other of two computers, enabling, at a given instant the setting up of the connection with only one of the two computers exclusive of the other without predetermined order of priority between the computers.
    Type: Grant
    Filed: December 28, 1973
    Date of Patent: January 20, 1976
    Assignee: Compagnie Industrielle des Telecommunications Cit-Alcatel
    Inventors: Yves Salle, Marcel Pincemin
  • Patent number: 3934229
    Abstract: Disclosed is a calculator having a basic pair of semiconductor chips respectively providing memory and computational functions and a third chip in combination therewith providing additional register and memory capacity. The basic chip pair generates system timing signals, flag signals and control signals which address the registers on the third chip and allow data to be written there into via the input/output data lines and data to be read therefrom via the input/output lines. The specific functions are effected upon the occurrence of the flag signal concurrently with a preselected timing signal.
    Type: Grant
    Filed: December 10, 1973
    Date of Patent: January 20, 1976
    Assignee: Texas Instruments Incorporated
    Inventors: Michael J. Cochran, Charles P. Grant, Jr.